多層技術設計之小型化高頻電路

Abstract

隨著材料及製程技術的進步，多層電路的開發配合高速及射頻電路的發展持續進行著，應用多層電路技術，更易於達成高速數位電路及射頻電路的小型化及高整合化。然而，相較於表面黏著元件，當電路元件內埋至多層電路後會產生不同的電氣特性，本篇論文首先探討在射頻電路應用中基本但卻重要的內埋電容及電感，應用多層電路架構及高介電常數材料，內埋電容可提供足夠的電容值範圍，但在內埋電感時，由於製程無法提供夠緊密的繞圈造成大量的磁漏，因此無法在有限的空間產生足夠的電感值。接著討論利用低溫共燒陶瓷製程技術，設計應用於USB 2.0產品的共模濾波器，相較於一般以磁性材料為主的繞線式共模濾波器，使用多層電路技術設計的共模濾波器可提供較低的差模訊號損失，此外，應用偏移線路的新架構而非完全重疊的線路來設計差模訊號線路組，可減少33%的零件厚度。為因應高速時脈及高速線路的不斷發展，用於控制訊號、時脈同步的延遲線路需求日益增加，接著討論的題目便是應用低溫共燒陶瓷製程技術設計多層的延遲線路元件，為了改善在微帶線/帶線型折線式延遲線路波形失真的問題，論文中提出以接地的防護線來設計小型化的三維多層延遲線路元件，比較應用帶線型折線式延遲線路和應用三維架構設計的延遲線路元件，同樣提供233 ps的延遲時間，多層架構設計之延遲線路可縮小至EIA 1206 的尺寸，省下2.34倍的電路板面積。論文最後探討上述三種以多層架構設計的元件，提出改進及可能的發展方向。

With advances in material and process technologies, developments of multi-layer circuit are enthusiastically pursued by both high-speed and RF communities. Using multi-layered technologies, the miniaturization and, subsequently, increasing level of integration of high speed digital and RF circuits are more easily realized. The embedded components, however, have different electrical characteristics as compared to the surface mount elements. In this dissertation, characterizations of embedded MIM capacitor and solenoid inductor, which are fundamental but important parts in RF systems, are performed first. With multi-layer structure and high dielectric constant material, the designed embedded capacitors can provide sufficient capacitance. But due to significant magnetic flux leakage present in the loosely wound embedded solenoid inductor structure, large inductance cannot be realized in a compact structure. This is followed by the design of a LTCC common-mode filter intended for use with USB 2.0 products. As compared to the wire-wound common-mode choke, the designed multi-layer common-mode filter produces lower insertion loss on differential-mode signal than conventional ferrite-based common-mode filter. Also, by using a novel offset architecture, as opposed to completely overlapped architecture, for the differential transmission pair, a 33% reduction of thickness is achieved in the design of a miniaturized common-mode filter with multi-layer LTCC technology. In view of increasing need of high-speed clock and data circuits to control their skew problems, a design of LTCC delay line is then conducted. To improve the waveform distortion associated with the microstrip/stripline-type meander delay line, a miniaturized high-frequency 3-D delay line with grounded guard traces is introduced. By means of 3-D structure, the 233 ps delay time, which requires extra board space amounting to a factor of 2.34 by stripline type meander delay line, can be shrunk into an EIA 1206 form factor. Conclusions on the three types of multi-layer component studied here and recommendations concerning potential improvements of these components are discussed, finally.