金氧半導體元件雜訊對射頻積體電路的影響

Abstract

本論文的目標在研究元件的雜訊在射頻電路設計中的角色。對低雜訊放大器而言，描述在不同的頻率範圍下，具有源極迴授式之低雜訊放大器技術已被印證其可行性。經由兩種不同的方法了解雜訊與輸入阻抗之變化情形，首先經由雙埠網路觀察最小雜訊指數和等效輸入電阻隨源極電感而產生的變化。其次，經由等效模型萃取出影響最小雜訊指數和等效輸入電阻之主要元素，在C頻段下使用此技術，可同時獲得具有負23分貝的優良輸入反射損失和1分貝的最小雜訊指數。封裝元件應用在此源極電感迴授式之頻率限制亦同時著墨。其次，使用聯電0.5um金氧半導體技術製作積體化低雜訊放大器，在偏壓3伏特和操作頻率2.4GHz下，信號增益12.5dB ，雜訊指數5.6dB和40mW的消耗功率。由於閘極電阻率較高，使得雜訊指數及訊號增益量明顯受到影響，因此在設計射頻積體電路晶片製作上需考慮低閘極電阻率之製程參數，提升電路操作性能。 另外，使用台積電0.35um金氧半導體技術製作積體化壓控振盪器亦被提出，他具有2GHz的振盪頻率，在3伏特偏壓下功率消耗為23.58mW且有9.1%頻寬調制。在晶片製作中，最佳化電感佈局設計不僅提升品質因素，更降低了相位雜訊。文中亦提出預測相位雜訊的計算法，經由量測結果得到在600KHz的偏移頻率下，其相位雜訊為 -115.5 dBc/Hz。依觀察，預測數值與量測數據相當吻合。

The goal of this thesis is to study the noise phenomenon and property of the device. And how noise applied to design the RF circuits. First, the noise figure to LNA is presented. The feasibility of the technique of source inductive feedback (SIF) for low noise amplifiers (LNA) design is examined in different frequency domains. The variations in noise and input impedance are obtained by two different approaches. One is from a noisy two-port analysis to observe the variation of Fmin and Rn , and the other is from equivalent circuit model to trace out the key element. Using ISF, the results with both good input return loss about -23dB and low minimum noise figure about 1dB at C band are demonstrated. The frequency limitations of the SIF technique in package devices are also addressed.Another circuit of 2.4GHz CMOS LNA was fabricated by the process of UMC 0.5um DPDM technology. It has 12.5dB gain and 5.6dB noise figure under 3V bias. Owing to the gate sheet resistance 30 Ohms/□ is so high that it affects the noise figure and signal gain. From the noise analysis of gate effect to LNA, it shows very match the noise level by taking gate resistance of the device into account. In words, choosing lower sheet resistance of poly gate is necessary to RF circuits. Secondly, the phase noise to VCO with 2GHz operating frequency is proposed. The fully integrated LC voltage controlled oscillator by TSMC 0.35um CMOS technology is demonstrated. It has 2GHz oscillation frequency, 23.58mW power consumption under 3V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring to phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculating data is about -115.5dBc/Hz at offset frequency 600KHz.