元件結構和製程條件對非晶矽薄膜電晶體的可靠度之效應研究

Abstract

在本篇論文當中，我們運用非晶矽薄膜電晶體(a-Si:H TFTs)為元件，分別從改變不同元件結構和製程條件來探討元件在施加不同的閘極和汲極偏壓應力(bias stress)下的不穩定現象。其中，這不穩定現象是由電荷攫取(charge trapping)和能態生成(state creation)這兩種不同的機制所共同造成。不穩定現象會隨著所施加電壓的不同造成不同程度的臨界電壓偏移 (threshold voltage shift) 。如果只在閘極施加偏壓應力，其臨界電壓偏移與通道長度並沒有關係；然而，同時在閘極和汲極施加高偏壓應力時，則可發現臨界電壓偏移會隨著通道長度增加而變大。更進一步，藉由施加不同的閘極和汲極偏壓應力來討論元件的不穩定現象，則發現在固定低的閘極偏壓應力下，其臨界電壓偏移會隨著汲極偏壓應力的增加而降低，但在固定高的閘極偏壓應力且汲極偏壓應力夠大時，臨界電壓偏移卻會隨著汲極偏壓應力的增加而提高。其現象主要是因自發熱效應使元件的不穩定現象變大。為進一步探討該自發熱效應(self-heating effect)，我們採用通道寬度為1504μm和通道長度為4μm的元件，改變其結構如直條形、指狀形、蛇形和多通道結構來探討此現象，研究發現在高的閘極和汲極電壓應力下，採用直條型搭配多通道之結構具有較少的臨界電壓偏移。另外，在指狀形的結構下我們改變多通道的通道間距，結果發現改變Y方向距離會比改變X方向距離之臨界電壓偏移來的小。其可利用一簡單的熱傳導示意圖來解釋該現象。此外，我們亦發現指狀形元件結構，在源極的指狀數量多於汲極指狀數量下，其臨界電壓偏移會比汲極指狀數量多於源極指狀數量之元件還少。進一步，我們利用最上層的金屬進行新的結構設計，並設計較厚之護層以使得上層之金屬不至於影響元件背通道的正常操作，我們發現在上層金屬連接汲極的元件結構下會有最少的臨界電壓偏移。 另一方面，藉由探討改變元件之閘極和源汲極之金屬厚度、非晶矽薄膜厚度和非晶矽薄膜沉積速度等不同條件，發現當增加源汲極金屬厚度時，將比傳統式與增加閘極之金屬厚度有較少臨界電壓偏移。再者，改變不同非晶矽薄膜厚度和沉積速率的實驗下(厚度為150μm 和 240μm，沉積速率為每分鐘46.2 nm 和168 nm )，發現低的薄膜沉積速度搭配厚的非晶矽薄膜元件具有較好的可靠度特性，但高厚度的非晶矽薄膜會導致垂直的通道阻值較高因而使電流相對較低。在此實驗中，亦發現低沉積速度的非晶矽薄膜電晶體在負電壓應力下會出現反轉現象 (turnaround phenomenon)，也就是臨界電壓會從正向偏移轉換成負向偏移。這是由於電荷攫取和能態生成相互作用的結果。 最後，進一步探討當元件在長時間的正電壓應力下，利用施加閘極之負偏壓應力來恢復元件之特性研究，我們發現本研究改變非晶矽薄膜厚度和非晶矽薄膜沉積速度四種條件在做負電壓的應力下，皆可使臨界電壓偏移減少。且我們可藉由使用多通道結構、新穎之結構、較厚之非晶矽厚度、和較低之非晶矽薄膜沉積速率來使的元件可達到更好的可靠度特性.

In this thesis, the instability issues of a-Si:H TFTs with various device structures and processes after prolonged different gate and drain bias stresses were investigated. It was found that the threshold-voltage shift results from the charge trapping and state creation is dependence on different conditions. Under gate bias stress only, the threshold-voltage shift is not dependent on channel width of a-Si:H TFTs. However, under high gate and drain bias stress, the threshold-voltage shift increases with enlarging the channel width. Moreover, we studied the instability with different gate and drain bias stresses. Under low fixed gate bias stress, threshold-voltage shift decreases with increasing drain-bias stress; while under high fixed gate- bias stress, the threshold-voltage shift becomes serious as the drain bias stress is large enough. It is due to that self-heating effect causes the instability of a-Si:H TFTs to be serious. To further discuss the self-heating effect, we used different structure of a-Si:H TFTs with W/L=1504μm/4μm such as stripe-like, finger-like, snake-like and multi-channel structures. The experiment results reveal that the stripe-like structure with multi-channel has least threshold-voltage shift than the others after prolonged high gate- and drain-bias stresses. Besides, devices with finger-like structure, we modified different X- and Y-distances between each multi-channel. We found that the modified Y distance has less threshold-voltage as compared to the modified X distance. This phenomenon can be explained by using a simple heat-transferring model. And, we also found if the number of source finger is larger than that of drain finger a-Si:H TFTs with finger-like TFT has less threshold-voltage shift. Moreover, we designed a novel structure with the top metal contacting to source, drain, or gate electrodes and used thicker passivation layer to get normal device operation in the back channel of a-Si:H TFTs. We found the structure with top metal contacting to drain electrode has least threshold-voltage shift among those structures. On the other hand, by changing the thickness of metal as well as the thickness and deposition rate of a-Si:H film, we found that devices with increasing thickness of drain/source have less threshold-voltage shift than both devices with conventional and increasing the thickness of gate metal. We also varied the thickness and deposition rate of a-Si:H film to discuss the reliability issues of a-Si:H TFTs (thicknesses of 150nm and 240nm, deposition rates of 46.2 nm/min and 168 nm/min). It shows that devices with lower a-Si:H deposition rate and thicker a-Si:H thickness have the best reliability. While devices with thicker a-Si:H layer have lower channel current due to its high vertical-channel resistance. We also observed that devices with low deposition rate have turnaround phenomenon of threshold-voltage shift during the negative bias stress, while devices with high deposition rate do not have this issue. Further results reveal that the turnaround phenomenon is greatly influenced by the charge trapped in SiNx and state created in the a-Si:H layer. Finally, we discussed how devices after prolonged positive gate-bias stress can be recovered electrical performance by using a negative gate-bias stress. In our research, we found using negative gate-bias stress can reduce threshold-voltage shift for all devices with varying the a-Si:H-film thickness and deposition rate. Moreover, the reliability of a-Si:H TFTs can be improved by using the multi-channel structure, novel device structure, thicker a-Si:H layer, and lower a-Si:H deposition rate.