完整後設資料紀錄
DC 欄位語言
dc.contributor.author李國葆en_US
dc.contributor.authorLee, Kuo-Paoen_US
dc.contributor.author陳科宏en_US
dc.contributor.authorChen, Ke-Hungen_US
dc.date.accessioned2014-12-12T03:00:58Z-
dc.date.available2014-12-12T03:00:58Z-
dc.date.issued2008en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009367542en_US
dc.identifier.urihttp://hdl.handle.net/11536/80090-
dc.description.abstract本文的目的是使用可規劃邏輯閘陣列(FPGA)來實現一個全數位式脈波寬度調變控制直流電壓轉換電路,建立控制系統的數學等效模型、電路特性及實現方式。 本文採用現成的類比到數位(ADC)積體電路(IC)元件來對輸出電壓取樣,而得到一個差值(Error),此差值輸出到一個預先完成的「比例、積分、微分控制器(PID)」的查表控制電路中,進而得到一個脈波寬度調變的輸出結果。此脈波寬度調變輸出結果提供給一個四相位的降壓轉換器(Four-phase Buck converter),來得到本文所要得到的電壓轉換結果。在全數位的控制電路當中,本文採用Verilog硬體描述語言(Verilog HDL)搭配Xilinx的ISE發展軟體及為希(ULINX)科技的FPGA硬體實驗板,來驗證本文的設計與性能。zh_TW
dc.description.abstractThe purpose of the thesis is to implement a fully digital pulse width modulation controlled DC to DC converter. This thesis is also aimed at building a mathematical effective module equal, circuit characterization and implementation to the fully digital pulse width modulation controlled DC to DC converter. The thesis uses a ready ADC device to sample the input voltage and output an Error. The Error sends to a pre-calculated lookup-table PID controller and output a pulse width modulation result. After the result processed by a four-phase buck converter, we can get the voltage converting result of the thesis. Here we use Verilog HDL and Xilinx ISE develop environment under ULINX FPGA board to verify the design and performance in the thesis.en_US
dc.language.isozh_TWen_US
dc.subject數位脈波寬度調變控制zh_TW
dc.subject比例積分微分控制zh_TW
dc.subject數位顫抖控制zh_TW
dc.subjectDPWMen_US
dc.subjectPIDen_US
dc.subjectDigital Ditheringen_US
dc.title四相位數位脈波寬度調變之交換式直流電源轉換器zh_TW
dc.titleFour-Phase Digital Pulse Width Modulation for Switching DC-DC Converteren_US
dc.typeThesisen_US
dc.contributor.department電機學院電機與控制學程zh_TW
顯示於類別:畢業論文