CMOS 24GHz混頻器與低雜訊放大器

Abstract

本論文研製之本論文提出操作頻率在24 GHz射頻前端接收器，經由國家晶片系統設計中心(CIC)委託台灣積體電路製造股份有限公司(TSMC)以0.18μm互補式金氧半導體製程技術來實現。此射頻前端接收器包含的電路有24GHz的降頻混頻器與24GHz低雜訊放大器。24GHz的降頻混頻器已經被完整的設計、製造與量測完成而24GHz低雜訊放大器尚在量測中。 24GHz的降頻混頻器量測結果顯示，模擬時候可以有4.5dB的轉換增益,因為佈局的模擬的疏失,使得轉換增益只有-4.5dB,不然預期。24GHz低雜訊放大器模擬有10dB的增益與3.7dB雜訊指數,於0.8V低電壓操作,消耗電流9.4mA。

In this thesis , we focus on 24GHz RF CMOS Mixer and Low Noise Amplifier has been proposed and fabricated in a 0.18μm CMOS technology supported by Taiwan Semiconductor Manufacturing Company via Chip Implementation Center(CIC). The 24GHz RF CMOS Mixer is completely designed, fabricated and measured, 24GHz Low Noise Amplifier is measuring. In 24GHz Mixer ,we implemented Marchand Balun by using TSMC 0.18μm CMOS technology process. measured results exhibit that the Mixer can operate well at 24-GHz frequency range. But is doesn’t achieve adequate performance due to the oversight of layout. In 24GHz Low Noise Amplifier ,we implemented cascade two Common Source stages by using TSMC 0.18μm CMOS technology process.