覆晶封裝在封裝與機板共同設計階段一個線長驅策及被範圍條件限制的訊號區塊擺放方法

Abstract

隨著先進製程技術快速發展之下， 越來越多的電路可以被整合在單一晶片裡，這樣的趨勢造成封裝設計與訊號之間的連接變得更為複雜。 然而，傳統打線封裝技術在一些特殊設計上已不敷實用，取而代之的是目前已被廣泛使用的覆晶封裝技術。 覆晶封裝設計裡在封裝與機板共同設計階段中，一般排放錫球的方式都是以資深工程師依經驗手動擺放，這是一個很費時又反覆的過程， 影響了產品上市的時間~(TTM)。因此，[1]以自動化程式產生面陣列引腳錫球圖~(Ball Grid Array,~BGA)，以利工程師做事後微調的動作， 大幅地減少這排放過程花費的時間。在這篇論文裡，我們展現了自動化產生面陣列引腳錫球圖的過程， 並且在封裝與機板共同設計階段提出一個被範圍條件限制的訊號區塊擺放改進方法並且使用模擬退火演算法~(Simulated Annealing Algorithm,~SA)來執行。 同時我們也對此特殊擺放的需求發展一個表示方法。我們提出的改進方法在訊號組態資訊參數設定上較有彈性，以及可以確保最小的封裝尺寸， 實驗數據結果顯示我們提出的改進方法優於論文~[1]的擺放方法。

With the advanced fabrication technique developing rapidly, more and more circuits could be integrated in a single chip. This trend will cause the complication in package designs and signal interconnection. However, the typical peripheral wire-bond design may not be proper for use in some particular designs, flip-chip becomes a better choice. In flip-chip design, engineers generally arrange the ball chart in the manual manner on experience in package-board codesign. This process is iterative, time-consuming and it will lengthen the time-to-market~(TTM) of products. [1] proposed a method of generating the BGA ball chart automatically by pin-block design and floorplanning, thus helped engineers respin the ball chart slightly and saved the arranging time dramatically. In this thesis, we exhibit the procedure of accomplishing the method of~[1] and improve the flooplanner in~[1]. The proposed pin-block floorplanner designates pin-out for flip-chip BGA package by using the range constraints, and it is based on simulated annealing algorithm. We also develop a representation for this special floorplanning requirement. It not only has flexibility on specifying critical parameters of the pin configuration, but also guarantees the minimum package size. Experimental results show that improved pin-block floorplanner can perform a better pin assignment than that in~[1].