低溫複晶矽薄膜電晶體之氟鈍化製程與可靠度的研究

Abstract

此論文提出多種氟鈍化(passivatation)技術以製作高效能且高可靠度的複晶矽薄膜電晶體(poly-Si TFTs)。此外，我們亦研究在電壓應力(electrical stress)測試下，複晶矽薄膜電晶體之開啟電流(On-current)及關閉電流(Off-current)的不穩定性。最後，我們利用高解析度的掃描式電容顯微鏡(scanning capacitance microscopy, SCM)系統開發出一種探測氧化層崩潰(oxide breakdown)點的技術。 首先，我們提出與現有製程具高度匹配性的四氟化碳電漿處理(CF4 plasma treatment)技術，用以製作高效能的固態結晶(solid-phase-crystallized)之複晶矽薄膜電晶體。利用此技術，氟原子可以有效地被導入複晶矽薄膜中以消除薄膜中的載子補獲態(trap states)，進而有效地提升元件特性。經由四氟化碳電漿處理的複晶矽薄膜電晶體具有好的臨限擺幅(subthreshold swing)、低的臨界電壓(threshold voltage)及高的元件開關電流比(On/Off current ratio)；其載子電致遷移率(field-effect mobility)也提升了22.8 %。此外，四氟化碳電漿處理也提升元件的抗熱載子(hot-carrier)破壞的能力。之後，我們在將此技術搭配準分子雷射退火(exciner laser annealing)，應用於製作高性能的雷射處理之複晶矽薄膜電晶體 (ELA poly-Si TFTs)。實驗結果證明氟電漿處理能有效地鈍化複晶矽中及氧化層與複晶矽界面上的缺陷。因此，元件的特性可獲得大幅的提升。最重要的是因為矽-氟的高強度鍵結能，經過熱載子應力(hot carrier stress)測試後，發現摻入氟原子的複晶矽薄膜電晶體具有較好的可靠度。另外，我們亦提出一種利用氟矽玻璃(fluorinated silicate oxide, FSG)當緩衝層的複晶矽薄膜電晶體製程。利用此方法亦可有效的鈍化複晶矽缺陷，進而大幅改善元件特性、均勻性及可靠度。其中，氟在氟矽玻璃中最佳的含量大約介於 2% 到 4% 間。 接著，本論文探討複晶矽薄膜電晶體在不同電壓應力測試下的開啟電流(On-current)及關閉電流(Off-current)的不穩定性。利用施加不同的閘極及汲極電壓來研究應力測試下所產生的元件劣化情形。經由結果我們歸納出，氧化層的捕獲電荷(trap charges)及複晶矽通道中的載子補獲態(trap states)之數量與空間分佈是造成開啟電流(On-current)及關閉電流(Off-current)的變化的最主要因素。我們利用此技術完成一個完整的模型以解釋複晶矽薄膜電晶體的開啟電流及關閉電流之不穩定性的原因。 在論文的最後，我們開發出一種利用掃描式電容顯微鏡(scanning capacitance microscopy, SCM)搭配原子力顯微鏡(atomic force microscopy, AFM)的探針掃描技術以研究氧化層的崩潰(oxide breakdown)現象。此技術可以清楚地掃描出氧化層崩潰點(breakdown spots) 的局部分佈。這些崩潰點因為具高度導通性(conductivity)因而顯示出非常低的微分電容值(dC/dV)訊號。由結果顯示出，氧化層的崩潰點的直徑大概為 6奈米(nm)到13.5奈米之間。此外，根據原子力顯微鏡的結果，我們亦發現氧化層的崩潰現象並不會造成其表面平坦度的改變。

In this thesis, various fluorine passivation techniques for fabricating high-performance and high-reliability polycrystalline silicon thin-film transistors (poly-Si TFTs) are proposed and discussed. In addition, the On-current (Ion) and Off-current (Ioff) instabilities of poly-Si TFTs under electrical stress are thoroughly investigated. At last, a new scheme by employing high-resolution scanning capacitance microscopy (SCM) is developed to scan the breakdown spots on oxide films. First, a process-compatible CF4 plasma treatment for fabricating high-performance solid-phase-crystallized (SPC) poly-Si TFTs is demonstrated. Using this technique, fluorine atoms can be introduced into poly-Si films to passivate trap states, and hence the performance of SPC poly-Si TFTs can be significantly improved. The fluorinated SPC poly-Si TFTs exhibit good subthreshold slope, low threshold voltage, and better On/Off current ratio. The fluorinated poly-Si TFT also shows approximately 22.8 % enhancement in the maximum field-effect mobility. Moreover, the CF4 plasma treatment also promotes the device’s hot-carrier immunity. Then, CF4 plasma treatment combined with excimer laser annealing (ELA) is proposed to fabricate high-performance ELA poly-Si TFTs. Fluorine can effectively passivate the trap states near the SiO2/poly-Si interface. With fluorine incorporation, the electrical characteristics of ELA poly-Si TFTs are significantly improved. The CF4 plasma treatment also improves the device reliability of ELA poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds. Another fluorine passivation technique is also proposed by adopting fluorinated silicate oxide (FSG) as a buffer layer. Experimental results reveal that the device performance, uniformity and reliability can be remarkably improved with appropriate fluorine content (2% to 4%) in the FSG layer. Then, the On-current (Ion) and Off-current (Ioff) instabilities of poly-Si TFTs are thoroughly investigated under various electrical stress conditions. The stress-induced device degradation is studied by measuring the dependences of Ion and Ioff on the applied drain/gate voltages. From the results, dissimilar variations of Ion and Ioff can be observed, which is attributed to the variances in the amount of trap charges in the gate oxide and the spatial distributions of trap states generated in the poly-Si channel. A comprehensive model for the degradation of Ion and Ioff in poly-Si TFTs under various electrical stress conditions is proposed. Finally, scanning capacitance microscopy (SCM), combined with atomic force microscopy (AFM), is employed to investigate the dielectric breakdown phenomena in SiO2 films. The localized breakdown spots can be clearly imaged by this technique. The breakdown spots exhibit signals with low differential capacitance (dC/dV) due to high conductivity. The diameters of these breakdown spots are from 6 nm to 13.5 nm. Moreover, according to the corresponding AFM images, their surface morphology shows little change after the occurrence of oxide breakdown.