高速序列傳輸之內建自我測試電路設計

Abstract

本論文提出一個高速序列傳輸之內建自我測試電路設計 (High Speed Serial Link Built-in Self Test Circuit Design) 電路，用來降低生產測試成本。利用數位控制延遲電路 (Digital Control Delay Line：DCDL) 產生特定相位之時脈，取樣並保持電路 (Sample and Hold：S/H) 抓取輸入的眼圖 (Eye Diagram) 訊號，與數位/類比訊號轉換器 (Digital-to-Analog Converter：DAC) 輸出的某特定電壓做比較，判斷眼圖有無張開至特定規格，由於不需要高速的測試儀器，可大幅降低測試成本。 高速序列傳輸之內建自我測試電路設計將至聯華電子股份有限公司 (United Microelectronics Corporation：UMC) 下線，所使用製程是 UMC 90nm 1P9M Logic / Mixed Mode Low-K SP-RVT Process 來實現。眼圖之抖動解析度為2.8ps，眼圖之振幅解析度為4.68mV，眼圖之振幅量測範圍為0~1.2V，完成眼圖之總量測時間為655G位元時間，核心電路的面積為270μm2 X 171μm2，模擬眼圖皆達到我們所預期的行為。

In this thesis, we propose a high speed serial link built-in self test circuit design for low-cost mass production. It includes a Digital Control Delay Line (DCDL) for clock delay adjustment, a Sample and Hold (S/H) module for capture the signal, a Digital-to-Analog Converter (DAC) to set up the compared level. Because it does not need high-speed tester, the test can be reduced significantly. The proposal high speed serial link built-in self test circuit is designed in an UMC 90nm 1P9M Logic / Mixed Mode Low-K SP-RVT Process. The jitter resolution for the eye diagram measurement is 2.8ps. The amplitude resolution is 4.68mV, and the amplitude range is ±600mV. The chip occupies a core area of 270μm2 X 171μm2, the post-simulation eyes diagram all reaches our anticipated behavior.