考慮製程變異下應用Bootstrap信賴區間模擬空間相關性

Abstract

隨著製程的技術進步及系統單晶片的到來，深次微米中的時序問題已越顯重要。傳統以 corner value 為基礎的時序分析將會導致預測的時序被過分低估。統計型靜態時序分析 ( Statistical Static Timing Analysis - SSTA) 就是利用統計的方式去描述這些製程偏差,把他們視為一些統計的隨機變數,然後利用他們去預測時序並且得到更準確的結果。SSTA 使晶片設計者能得以將時間餘裕(timing margin)及良率(yield)做最佳化以提升晶片效能和可靠度。不同於其它論文之模型探討，本文考量實際製程變異及晶圓應用的可行性，提出一個實用且新穎的路徑學習重複取樣的方法論(path-based learning methodology with Balanced Bootstrap re-sampling ) 。此方法不須作任何timing model的假設，只須從現有寶貴的晶圓量測資料中，重覆作re-sampling learning的動作，即可得到準確path delay的空間相關性(spatial correlations)之推論。同時藉由建立信賴區間的方式，可得到path delay correlation 和 path distance兩者之間的關係和趨勢，由此推論path distance變化時，會有多少path delay的變化。此方法在晶圓廠有兩個方面可應用:(1)在先進晶圓製程階段，使用re-sampling 方法，可對有限的晶圓量測資料，快速建立近似的統計型時序模擬器。 (2)在成熟晶圓製作階段，使用路徑學習方法，觀察測試晶片的量測資料，可取得統計型靜態時序分析(SSTA)之建模(modeling)。

With the advances to nanometer technologies and SOC, the process variation plays a more important in the future. Traditional corner value timing analysis becomes less effective and grossly conservative. Statistical timing models and simulation methods are required to capture these variation effects. The methodology of statistical timing analysis that characterizes time variables as statistical random variables offers a better approach for more accurate timing predictions. SSTA enable designer to setup and hold Timing Margins to optimize and improve the performance and reliability. The thesis considers real process variations and fabrication implementation designs a practical test chips and presents the implementation of a novel path-based learning methodology with Balanced Bootstrap re-sampling that accounts for process variations and their spatial correlations. It doesn’t need timing model hypothesis and make the accurate timing spatial correlation inference from fabrication measurement data. By constructing the confidence interval of the spatial correlation, we can get correlations and predictions for path delay and path distances. By this, we can know how many path distance changes will cause how many path delay correlation changes. It can be applied for two purposes. First, the bootstrap re-sampling can be used to produce a fast and approximated simulator for statistical timing simulations in the advanced production phase. Secondly, this path-based learning can be used as a vehicle to derive statistical static timing analysis (SSTA) based on observed measured data from the test chips in mature production phase.