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DC Field | Value | Language |
---|---|---|
dc.contributor.author | 陳映頻 | en_US |
dc.contributor.author | Ying-Pin Chen | en_US |
dc.contributor.author | 陳方中 | en_US |
dc.contributor.author | Fang-Chung Chen | en_US |
dc.date.accessioned | 2014-12-12T03:02:07Z | - |
dc.date.available | 2014-12-12T03:02:07Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009396502 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/80389 | - |
dc.description.abstract | 本研究以沈積溫度為變因,探討五環素未經歷嚴重晶相變化時,晶粒形貌對薄膜電晶體電性的影響。除了部分嚴重相變與高於表面處理物玻璃轉移溫度的元件外,電洞遷移率與橫向晶粒都有隨溫度升高而增加的趨勢。透過電阻萃取的方式,我們得到下述結果:通道電阻隨溫度升高而下降,此為升溫增大橫向晶粒所致;接面電阻亦隨晶粒增大而降低;塊體電阻則與晶相變態的嚴重程度有關。此外,基板經表面處理的電晶體,即使表面晶粒相似也可大幅提昇遷移率。 對表面處理的基板而言,平躺五環素的發生是一重大特徵。過去的研究仍未明確指出此位向的分子對傳輸機制有何影響。另外,文獻表示五環素於二氧化矽基板之縱向成長為丘狀成長,此將造成較深的縫道(晶界),而丘狀形貌也是Ehrlich-Schwoebel能障存在的表徵。 我們使用AFM觀察8nm厚(五層分子)的五環素試片,發現經表面處理的試片,其五環素晶界間有模糊化的現象,這暗示了當平躺分子存在時,E-S能障降低。我們認為平躺五環素的存在能提昇遷移率的原因,在於此時五環素塊體的晶緣(step edge),其E-S能障較低,使得晶界填補較為容易。因此,即使平躺位向之分子可能導致基板表面的排列較亂,但遷移率仍舊可提升,這說明了晶界對遷移率而言仍為最具支配力的因素。 | zh_TW |
dc.description.abstract | By varying the temperature during the deposition of pentacene, the effect of substrate temperature on the electrical performance of OTFTs, without serious disturbance of phase transition of pentacene is investigated. First, the channel resistance is sensitive to the deposition temperature due to the difference size of grains. Second, the contact resistance reduces with increasing deposition temperature, which is likely attributed from the difference of the molecular orientation. Finally, the bulk resistance is more fluctuant to the deposition temperature for P□MS-treated devices, whereas the case for HMDS-treated ones is less fluctuant probably arising from phase boundary. Additionally, the existence of flat-lying pentacene is an important characteristic for the treated devices. However, it is unclear what role the in-plane π system plays. Based on Ehrlich-Schwoebel barrier effect, mound growth governs the vertical evolution, forming deeper crevices. According to the AFM images of initial layer, it suggests that flat-lying pentacene could lower the E-S barrier, leading to shallow boundaries. Consequently, effect of grain boundary is still the most dominant factor to the mobility. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 沈積溫度 | zh_TW |
dc.subject | 晶界 | zh_TW |
dc.subject | 相變化 | zh_TW |
dc.subject | 表面修飾 | zh_TW |
dc.subject | 平躺位向 | zh_TW |
dc.subject | 電阻萃取 | zh_TW |
dc.subject | deposition temperature | en_US |
dc.subject | grain boundary | en_US |
dc.subject | phase transition | en_US |
dc.subject | surface treatment | en_US |
dc.subject | flat-lying | en_US |
dc.subject | transfer line method | en_US |
dc.title | 五環素沈積溫度對有機薄膜電晶體電性影響之研究 | zh_TW |
dc.title | Effect of Deposition Temperature on the Device Properties of Pentacene Thin-Film Transistors | en_US |
dc.type | Thesis | en_US |
Appears in Collections: | Thesis |
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