完整後設資料紀錄
DC 欄位語言
dc.contributor.author林俊文en_US
dc.contributor.authorChien-Wen Linen_US
dc.contributor.author戴亞翔en_US
dc.contributor.authorYa-Hsiang Taien_US
dc.date.accessioned2014-12-12T03:02:10Z-
dc.date.available2014-12-12T03:02:10Z-
dc.date.issued2006en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009396517en_US
dc.identifier.urihttp://hdl.handle.net/11536/80406-
dc.description.abstract複晶矽薄膜電晶體(poly-Si TFT)最近幾年在液晶顯示器(AMLCD)及有機發光二極體(AMOLED)顯示器應用中,由於其優異的元件特性,而成為眾所注目的焦點。與非晶矽薄膜電晶體(a-si TFT)相比複晶矽薄膜電晶體的電子遷移率高了數百倍,所以可以利用於當面板週邊電路和畫數開關。然而,先前關於可靠度元件模型的研究多聚焦在電流-電壓特性,而關於電容-電壓劣化行為的討論較少。 本文探討低溫多晶矽(LTPS)薄膜電晶體(TFTs)在直流偏壓(DC Stress)之下,源極和閘極之間的電容(CGS),汲極和閘極之間的電容(CGD)的變化行為。在直流偏壓劣化現象中,熱載子效應與及自發熱現象為主要劣化機制,本文探討LTPS TFT在此兩偏壓條件下的劣化行為,發現其電容特性呈現明顯頻率相依性。也比較電容-電壓和電流-電壓之間在直流偏壓後的特性曲線變化,判別在直流偏壓後缺陷產生的位置與種類。在不同條件下,探討對薄膜電晶體產生的劣化機制。利用電路學的觀念,我們發展出一個新的薄膜電晶體電路模型,並且利用這個電路模型,解釋在不同偏壓條件下的電容-電壓與電流-電壓之間的關係。新建立的薄膜電晶體電路模型,可以放入模擬軟體當中,令設計者在使用時,更快速及便利的瞭解元件的特性,掌握良好的設計條件,完成更複雜的電路設計和節省設計時間,期望對於幫助設計單面板系統整合的電路有更先進的突破,以利更高階面板技術的發展,讓顯示器產業達到更好更符合人眼視覺的境界。zh_TW
dc.description.abstractPolycrystalline silicon (poly-Si) thin film transistors (TFTs) have recently attracted much attention in the application on the integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode (AMOLED) displays. However, most of the previous reseaches focus on the current-voltage characteristics, while the discussion about capacitance - voltage degradation is few. In this thesis, the degradation of low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) under DC stress is investigated with the measurement of the capacitance between the source and the gate (CGS), as well as the capacitance between the drain and the gate (CGD). The main degradation mechanisms of the DC stress are hot carrier effect and self-heating effect. This work focuses on the C-V behaviors of the LTPS TFTs with these two mechanisms and discovers that the C-V curves exhibit apparent frequency dependence. For the different stress conditions, the degradation mechanisms in the thin film transistor are discussed. With the concepts of circuitry, we develop a new thin film transistor electric circuit model, and explain the changes in adds under the different stress conditions in the C-V and I-V behaviors. The newly established thin film transistor electric circuit model can put in the middle of the simulation software to help designers with faster and convenient understanding device’s characteristics and design conditions. Hence, the designers can compute a more complex electric circuit within shorter design period to achieve the target of having an advanced breakthrough in designing system on panel (SOP) circuit. On the other hand, the technology development can help the display panel show the vivid images than the present product.en_US
dc.language.isoen_USen_US
dc.subject薄膜電晶體zh_TW
dc.subject電容zh_TW
dc.subject熱載子效應zh_TW
dc.subject自發熱現象zh_TW
dc.subject低溫多晶矽zh_TW
dc.subject頻率zh_TW
dc.subjectTFTen_US
dc.subjectCapacitanceen_US
dc.subjecthot carrier effecten_US
dc.subjectself-heating effecten_US
dc.subjectLTPSen_US
dc.subjectfrequencyen_US
dc.title低溫多晶矽薄膜電晶體直流偏壓下電容-電壓特性之研究zh_TW
dc.titleStudy on the C-V characteristics for LTPS TFTs under DC stressen_US
dc.typeThesisen_US
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