完整後設資料紀錄
DC 欄位語言
dc.contributor.author劉燕霖en_US
dc.contributor.authorYen-Lin Liuen_US
dc.contributor.author郭建男en_US
dc.contributor.authorChien-Nan Kuoen_US
dc.date.accessioned2014-12-12T03:02:12Z-
dc.date.available2014-12-12T03:02:12Z-
dc.date.issued2006en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009411502en_US
dc.identifier.urihttp://hdl.handle.net/11536/80417-
dc.description.abstract本篇論文的目的,主要在設計適用於低電壓操作及低功率消耗之前端接收電路,以應用於無線感測網路。共實現兩顆晶片。第一顆晶片為一低功率混頻器,藉由將轉導級與相位分離器整合的方式節省功率消耗,並且採用折疊式架構降低偏壓要求。轉導級之差動相位輸出、輸入匹配條件與雜訊輸出均加以分析。量測結果顯示,設計之混頻器消耗2mW功率,在1V偏壓下有10.4dB之電壓轉換增益,11dB之輸入返迴損耗及3.8dBm之輸入第三階交會點。第二顆晶片為一前端接收電路,包含有低雜訊放大器、混頻器以及將此兩級交流耦合之變壓器。設計之電路如折疊式架構,適用於低偏壓操作。並且,利用變壓器將單端信號轉換為差動信號,進一步省去相位轉換所需之功率消耗。論文中針對放大器之偏壓與穩定度、變壓器操作於共振模式,產生電流耦合增益之條件,均加以分析設計。量測結果顯示,此前端電路在0.6V偏壓下有12dB的電壓轉換增益,16.9db之輸入返迴損耗以及-2.8dBm之輸入第三階交會點,而此電路之功率消耗僅有0.29mW。zh_TW
dc.description.abstractThis thesis aims at design of a low-voltage low-power receiver front-end circuit applicable to wireless sensor networks. Two chips are realized. In the first chip, a low-power double-balanced mixer is designed in a folded topology. A transconductance stage with phase splitting function which is composed of a common-gate and common-source transistors is adopted for low power consideration. Output balanced condition, input matching, and noise of the transconductance stage are analyzed. Realized in 0.18-um CMOS technology, the measured input return loss and voltage conversion gain are 11dB and 10.4dB, respectively. The input third-order intercept point (IIP3) is 3.8dBm while consuming 2mW from a 1V supply. In the second chip, a receiver front-end circuit is designed for low supply voltage as low as 0.6V. The circuit consists of a low noise amplifier, switching stage, and on-chip transformer which provides AC coupling between stages connected to it in a folded structure. The transformer is designed not only to convert single-ended signal into differential form without excess power consumption, but also to operate in resonant mode to have current transfer gain. The power consumption of the circuit is effectively cut down. Also, a figure of merit for bias consideration and stabilization design for LNA is analyzed for the optimum design condition under low supply voltage case. The measured input return loss and voltage conversion gain are 16.9dB and 12dB, respectively. The input third-order intercept point (IIP3) is -2.8dBm while consuming only 0.29mW from a 0.6V supply.en_US
dc.language.isoen_USen_US
dc.subject無線感測網路zh_TW
dc.subject低電壓zh_TW
dc.subject低功率zh_TW
dc.subject射頻前端接收電路zh_TW
dc.subject低雜訊放大器zh_TW
dc.subject混頻器zh_TW
dc.subject變壓器zh_TW
dc.subjectwireless sensor networken_US
dc.subjectlow voltageen_US
dc.subjectlow poweren_US
dc.subjectreceiver front-enden_US
dc.subjectlow noise amplifieren_US
dc.subjectmixeren_US
dc.subjecttransformeren_US
dc.title應用於無線感測網路之低電壓低功率5-GHz射頻前端接收電路設計zh_TW
dc.titleLow-Voltage Low-Power 5-GHz Receiver Front-End Circuit Design for Wireless Sensor Networksen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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