緩衝層與經氫氣回火矽晶圓對具氮化矽覆蓋層之形變N型金氧半場效電晶體之元件特性及可靠度之影響

Abstract

在本研究中，我們探討了使用氮化矽覆蓋層與四乙氧基矽烷(TEOS)氧化矽緩衝層對於具有形變通道的n-型電晶體的性能影響與可靠度分析。元件分別製作於CZ晶圓與經氫氣回火矽晶圓(Hi-wafer)。另外，元件通道植入氟離子對電晶體的性能影響與可靠度分析亦一並討論。結果顯示出元件製作於Hi-wafer上，其四乙氧基矽烷氧化矽緩衝層對元件不會造成特性的衰退；然而，元件製作於CZ-wafer上卻造成特性的衰退，以上的差異是由於Hi-wafer的良好表面品質及較少的基板含氧量。另一方面，氟離子的通道植入對於元件製作於CZ-wafer上造成特性明顯的衰退，例如：轉移電導及次臨界斜率，然而採用Hi-wafer作為基板並不會產生以上的負面影響。沉積氮化矽覆蓋層所造成的熱預算使通道中的硼離子再擴散進而消除逆短通道效應，但是卻會使多晶矽空乏現象變嚴重。我們發現氫氣是對具有形變通道元件產生可靠度衰退的主要原因，而四乙氧基矽烷氧化矽緩衝層可有效阻擋沉積氮化矽覆蓋層所產生的氫氣擴散進入通道及二氧化矽與矽基板間的介面。當與對照條件做比較時，無論是在CZ晶圓或是在經氫氣回火矽晶圓，於閘極上方所沉積的氮化矽覆蓋層皆對元件熱電子衰退特性造成不利影響。然而，在沉積氮化矽覆蓋層前先沉積四乙氧基矽烷氧化矽緩衝層，雖然其熱電子衰退特性比對照條件差，但明顯地改善元件可靠度。此外，元件通道植入氟離子的確對可靠度造成明顯的改善。

In this thesis, the effects of both the Si3N4 layer capping over the gate and the hydrogen-blocked TEOS buffer layer inserted prior to the Si3N4 deposition, on the NMOS device characteristics as well as the correlative hot-electron degradation were investigated. The devices were built on two kinds of the substrates, namely, Cz and Hi-wafers. Besides, the influences of the F channel implant on both fundamental performance and the related reliability of the fabricated devices were also explored. For devices on the Hi-wafer, the buffer layer would not degrade the device performance. On the contrary, the buffer layer for devices built on Cz wafers would degrade the performance. Such disparity is attributed to the better surface quality of the Hi wafers. On the other hand, the F channel implant draws significant impacts on the device performance for devices built on Cz wafers, such as degradation of Gm and S.S. When Hi wafers were used as the starting substrates, such negative impacts could be relaxed. These findings highlight the merits of Hi wafers over that of Cz wafers. The thermal budget associated with the deposition of the Si3N4 capping layer could help redistribute the segregated boron dopants in the channel and alleviate the reverse short-channel effect, although the poly-depletion effect becomes worse. More importantly, we found that hydrogen species is the primary culprit for aggravated reliabilities in strained devices. The TEOS buffer layer could effectively block the diffusion of hydrogen species from Si3N4 into the channel and interface of Si/SiO2 during the Si3N4 deposition and subsequent thermal cycles. The hot-electron degradation is adversely affected when the Si3N4 capping layer is deposited over the gate as compared with the control samples, regardless of the types of wafers. When a TEOS buffer layer was inserted prior to the Si3N4 deposition, although still worse than the control ones, significant improvement in resistance to the hot-carrier degradation over that without buffer is achieved. Besides, with the assistance of the F channel implant, the hot-carrier degradation of devices is obviously improved.