電漿處理對雙閘極奈米線多晶矽薄膜電晶體影響之研究

Abstract

在本論文中，利用「由上而下」(top down)方式製作雙閘極奈米線薄膜電晶體。實驗中利用固相結晶法(SPC)製作多晶矽奈米線通道，並使用氨氣或氮氣電漿處理，以大幅增進材料及元件的效能。由實驗結果可知，雙閘極中的上閘極(top gate)較主閘極(main gate)有較優越的控制力；與單閘極奈米線薄膜電晶體相較，由於上閘極的加入大幅提升通道中的導通面積，進而增進電晶體的驅動電流。另外，更可利用在雙閘極上加不同偏壓來調變電晶體的導通臨界電壓，進而具有函數化(functional)的功能。本論文中，將雙閘極奈米線薄膜電晶體操作在上閘極模式(top gate mode)，主閘極模式(main gate mode)及雙閘極模式(double gate)，分別測量其電性並萃取其活化能，進一步討論其導通及漏電流機制和電漿處理所造成的影響。 本論文中，並探討利用高介電質材料覆蓋單閘極奈米線電晶體，以藉由高介電值的邊際效應(fringing effect) ，來大幅增進元件電性。

In this thesis, we utilize the top-down approach to fabricate double-gated nanowire thin film transistor. Solid-phase crystallization was employed to grow polycrystalline-silicon nano-channel, and NH3 or N2 plasma was used to improve the material quality and device performance. From our experimental results, the top gate of double-gated nanowire thin film transistor has superior controllability over that of the main gate. Compared with the single-gated nanowire thin film transistor, the double-gated nanowire thin film transistor depicts higher drive current with larger conducting area by the incorporation of top gate. In addition, we also extract the activation energy for the double-gated nanowire thin film transistor operated in the top gate mode, main gate mode or double gate mode, respectively. The mechanisms of ON-state and OFF-state currents and the effect of the plasma treatments were investigated. In this thesis, we also explore the possibility of using the fringing field effect to enhance the device performance by passivating the single-gated nanowire thin film transistor with high dielectric constant material.