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dc.contributor.author詹仁嘉en_US
dc.contributor.authorRen-Jia Chanen_US
dc.contributor.author郭治群en_US
dc.contributor.authorJyh-Chyurn Guoen_US
dc.date.accessioned2014-12-12T03:02:39Z-
dc.date.available2014-12-12T03:02:39Z-
dc.date.issued2008en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009411583en_US
dc.identifier.urihttp://hdl.handle.net/11536/80498-
dc.description.abstract中文摘要 近年來次微米乃至奈米Si CMOS應用於通訊產品,已成為極重要之技術研發領域。而RF IC為通訊產品中最重要的bulding block,其設計面臨諸多問題與挑戰,其中on-chip電感設計與模擬,成為Si CMOS RF IC最佳化設計之關鍵技術。電感設計最重要的參數為品質因子(Q)、共振頻率(fSR)與面積等。On-chip電感往往消耗大部份晶片面積,造成單晶片電路面積微縮之瓶頸。再者On-chip電感Q值的特性往往被矽基板損耗侷限,導致Q值不佳而使電路無法達到更高頻,因Layout的不對稱也會造成port-1 與port-2可達的Q值不相等,造成最佳化設計之困難。此外,On-chip電感模型的準確度是決定設計最佳化的一關鍵因子,往往設計者所模擬與量測的結果不一致,有許多問題皆出在元件模型的準確度,已有許多文獻提出討論,並且量測的結果直接影響汲取參數的可靠性與準確度。至於電感結構設計,對稱性已成為另一重要參數,對於廣泛使用之差動式電路設計(differential topology),有極大影響。 本研究主題為利用0.13□m RF CMOS製程技術設計新的對稱電感,以應用於V-band高頻微波電路。在我們的設計中,所有尺寸的量測特性均符合共振頻率fSR高於80 GHz的寬頻表現而且高於預訂規格的70GHz,HFSS模擬器的電磁模擬和本研究所發展的等效電路模型enhanced T-model均可正確模擬高達110 GHz的寬頻特性,而利用本研究團隊之前發展的簡單分析模型可以準確的預測不同尺寸的共振頻率fSR。 透過設計小電感之實習我們可以發現一些關鍵的問題,例如集膚效應和鄰近效應為限制Q值之關鍵物理機制、高頻訊號的輸入和接地環的位置決定了電磁模擬的準確性、超高頻率的量測、和去寄生效應的方法。藉由理論分析來探討金屬線圈或是繞線在高頻操作下的能量損耗並且導致Q值的下降。推導分析模型來計算集膚效應和鄰近效應所造成的額外電阻值 和 ,我們所推導的模型包含頻率和幾何材料參數等之相依性,可以預測電感輸入端的阻抗Re(Zin),並且有效輔助寬頻電感的最佳化設計。zh_TW
dc.description.abstractAbstract Si RF CMOS has become a vital technology to realize a single-chip communication integrated circuit. On-chip inductors are one of key elements, which will determine RF circuit performance in terms of gain, power, and noise. However, the on-chip inductor design faces several challenges, such as broadband and high-Q, as well as area estate. The major difficulty comes from the energy loss associated with low resistivity of the silicon substrate. The lossy substrate introduces challenges, not only in performance optimization but also in simulation and modeling. Furthermore, 2-port symmetry is one more important feature, which is desired for the widely used differential circuits for low noise and high gain design. In this thesis, new symmetric inductors targeting for applications in V-band microwave circuits have been designed and fabricated in 0.13□m RF CMOS process. The measured characteristics can meet broadband performance with fSR higher than 80 GHz for all dimensions in the design, which is above the target of 70GHz. EM simulation (HFSS) and the developed equivalent circuit model (enhanced T-model) can simulate the broadband characteristics over 110 GHz. A simple analytical model previously derived from T-model can precisely predict fSR associated with various dimensions. Some critical issues emerge from this practice on small inductor design, such as Q limitation due to skin effect and proximity effect, EM simulation accuracy determined by RF signal injection and guard ring placement, ultra-high frequency measurement, and de-embedding methods. A theoretical analysis has been performed to explore the mechanisms responsible for the energy losses in metal traces or coils under a high frequency operation, and the introduced Q degradation. Analytical models have been derived for calculating the excess resistances, namely and corresponding to skin effect and proximity effect. The derived models incorporating frequency dependence, and geometry as well as material parameters can predict the input impedance Re(Zin) and guide an optimal design for broadband inductors.en_US
dc.language.isoen_USen_US
dc.subject電感zh_TW
dc.subjectInductoren_US
dc.subjectproximityen_US
dc.subjectskinen_US
dc.subjectModelen_US
dc.title單晶片寬頻電感設計以及等效電路模擬及分析zh_TW
dc.titleA Broadband On-Chip Inductor, Modeling and Analysisen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis


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