形成矽化鎳時在矽化鎳與矽接面處離子活化相關研究

Abstract

在先進互補式金氧半導體元件裡，當接觸尺寸縮小至奈米等級，源極及汲極的接觸電阻也會隨之增加。因此，金屬矽化物的技術應用在源極及汲極已經被開發用來同時降低接觸電阻及接面寄生電阻。在奈米金氧半場效電晶體的製造中，矽化製程是必須的，為了抑制源極及汲極的超淺接面形成所產生的短通道效應。所以，是否具有與矽基材完好介面特性的金屬矽化物，是在製造奈米尺寸的元件時重要的製程考量。在本論文中，我們主要探討離子佈植入矽化鎳再經由後續不同條件的退火製程後，所呈現出的活化量及電特性的研究。吾人結合離子佈植入矽化鎳和固態磊晶再成長的概念來達到低溫在介面處的高活化特性，此結果和吾人準備的傳統高溫退火試片相比較，發現在550度時的片電阻值即可與傳統高溫所得之片電阻值相當，此外，透過I-V和C-V的量測結果，我們可以對我們所製作的接面做理想因子和介面活化濃度的推算，總和所有的實驗結果，此低溫活化的特性是很有潛力取代傳統的高溫退火已獲得高活化的製程。

In advanced CMOS devices, as contact dimensions scale down to nanometer range, contact resistance of source and drain is increased correspondingly. As a result, the technique of metal silicides for poly gate and source/drain has been developed to reduce the contact resistance and the parasitic junction resistance as well. In nanometer MOSFET fabrication, this silicidation process requires considering to suppress short channel effect (SCE) when forming the ultra shallow source and drain junction. Therefore, metal silicides owning a perfect interfacial property with Si above an ultra-shallow junction is considered as a critical module toward the realization of nano-scale CMOS. In the thesis, we want to know the amount of activation and electro-characteristics by different thermal process. The experiments shows that nickel silicide interface dopant activation improved by two-step rapid thermal annealing (RTA) process. We combined the concept of implant into silicide (IIS) and solid phase epitaxial regrowth (SPER) to lowering the process temperature. Compared with the conventional samples, the results for doping interface had nice sheet resistance at RTA 550℃. By means of I-V and C-V method, we could also discuss the ideality factor and interface dosage. The overall results can promote the low temperature activation and have the potential to replace conventional high temperature anneal.