IEEE 802.16e OFDMA 下行通道估測技術之探討與數位訊號處理器實現

Abstract

正交分頻多工(OFDM)技術已經成功地被應用在普遍數位通訊的應用中。採用OFDM的主要原因之一是可抵抗對於多重路徑干擾的效應。我們著重在IEEE 802.16e OFDMA下行的通道估測部分，且用數位訊號處理器去實現通道估測的機制。此數位訊號處理器的環境是Freescale Semiconductor的MSC8126ADS，是個擁有四個運算核心的多工處理器。 我們探討了三種通道估測的方法，一個是二維的線性內插，一個是二維的非線性內插，另一個是最小平方法(Least-squares)。在通道被前面兩種方法估測出來後，我們用最小平均平方誤差等化器的方法去減少在移動的環境所造成的載波間互相干擾(ICI)。我們分別在靜態及時變的Rayleigh通道上驗證我們的模擬模型。 至於數位訊號處理器的部分，在運算復雜度與效能之間的做最有利益的選擇，所以只採用簡單的二維線性內插法，可以達到很好的速度之外，也有可以接受的結果。為了增加執行的速度，我們將寫定點數運算的C程式去應用在數位訊號處理器上面。

Orthogonal frequency division multiplexing (OFDM) has been successfully applied to a wide variety of digital communications applications over the past several years. One of the main reasons to use OFDM is its robustness when facing channel multi-path dispersion. We focus on the OFDMA downlink channel estimation with a reference framework of IEEE 802.16e. Also, we implemented OFDMA downlink channel estimation schemes on a digital signal processor. The DSP is a Freescale Semiconductor’ MSC8126ADS, which is a four-core signal processor. We study three channel estimation methods; two are based on two-dimensional linear and non-linear interpolations, then another is formulated as a least squares problem. After channels are estimated by aforementioned methods, we used a block MMSE equalizer to reduce inter-carrier interference in mobile environment. We verify the performance with numerical simulations on both static and time-variant fading channels. As for the DSP implementation, a two-dimensional linear interpolation is chosen due to its computational complexity. The DSP implementation is also carried out with fixed point formats.