極低功率且高效能之32位元嵌入式處理器設計伴隨JPEG解碼器系統

Abstract

本論文提出一個極低功率且高效能之32位元嵌入式處理器ACARM7(ACademic ARM7)的研究成果報告。其一，此一處理器有較佳的優異性能。此處理器是以ARM V4指令集實作，所以此指令集能使用ADS(ARM Developer Suite)的編譯器將高階程式語言(C,C++)編譯成組合語言，再將其組譯為可供ACARM7使用的機器語言，以顯示出此處理器的高使用性。經過與原廠ARM7TDMI相比，此處理器不但所消耗的功率更少，所使用的邏輯閘更少，而且操作時脈更為快速。其二，本論文提出一套完整且嚴謹的驗證流程。此流程既能在近10億個模擬週期的比對之下確保其功能行為之正確性，又能確保其合成為低階邏輯閘電路之後整個轉換正確性。其三，本處理器亦可供做JPEG解碼器系統。通過此驗證流程之後，此處理器之設計被燒錄在FPGA之上，再使用ARM926EJ-S Versatile發展板系統，以完成JPEG解碼器系統。 總之，本處理器無論在效能、面積、與功率等方面的比較都勝過ARM7TDMI；此論文提供一套完整且嚴謹的處理器開發驗證流程，以確保更佳之正確性；本處理器還燒錄在FPGA之上供做JPEG解碼器系統，以展示其提供良好的應用性。

This thesis presents the research result of an ultra low-power and high-performance 32-bit embedded processor with JPEG decoder system. This processor is named ACARM7 (ACademic ARM7). The ISA (Instruction Set Architecture) of ACARM7 adopts the ARM V4 architecture. Hence the ADS (ARM Develop Suite) can be directly used. ADS can first be used to compile the high level programming language (C, C++) written by users to the assembly language, and then can assemble the assemble language to the low level machine code for ACARM7 use. It indicates the high usability of ACARM7. Compared with ARM7TDMI, the power consumed by the proposed processor is lower; the gate-count of the proposed one is less; and the performance is better. Meanwhile, this thesis also provides a thorough and rigorous verification flow which assures both the correctness of functional behavior of the proposed processor design after more than two billion simulation cycle comparisons and the synthesis correctness of synthesized gate-level netlist circuit. Moreover, the proposed processor is mapped onto the FPGA and integrated within the ARM926EJ-S Versatile Development Board to implement a JPEG decoder system. Based on the experiment result obtained by this research, the higher performance, the smaller area, and the lower power are all the advantages of the proposed processor compared with ARM7TDMI. The thesis also proposes a thorough and rigorous processor verification flow. Moreover, the high applicability of the proposed processor is demonstrated by mapping it into an FPGA for implementing a JPEG decoder system.