新穎三閘極電晶體與薄膜電晶體之製程技術與特性研究

Abstract

在本論文中，吾人針對矽化鎳(NiSi) 應用於奈米覆晶矽(SOI)三閘極元件 (TGFETs) 與低溫複晶矽薄膜電晶體 (Low Temperature poly-Si TFTs) 之製程技術與元件特性分析進行研究，涵蓋內容包括了不同基板上矽化鎳薄膜熱穩定性，矽化鎳側向成長長度控制之研究，低溫之離子植入矽化鎳 (ITS) 技術應用於新穎覆晶矽奈米三閘極元件源/汲/閘極之研究，通道寬度、側閘極電壓、側閘極深度與背閘極電壓對三閘極元件可靠度影響之分析，最後吾人也驗證了低溫之離子植入矽化鎳技術與低溫沉積之高介電常數薄膜(HfO2)在可運用於面版上系統(SOP)之新穎低溫複晶矽薄膜電晶體的研製。 首先，在本論文中，我們驗證了在氧化矽基板(SiO2) 上之矽化鎳薄膜，因無多餘之矽成分，所以有較佳之熱穩定性。同時，運用了特殊之四端點片電阻測試結構也驗證了運用兩階段退火方式可以有效控制矽化鎳之側向成長長度。 其次，我們更將低溫兩階段退火(300oC+600oC)的矽化鎳薄膜與低溫離子植入矽化鎳 (ITS) 製程運用於新穎25奈米覆晶矽三閘極元件之源/汲極部分。此新穎元件有數個優異之製程與電特性：(1) 因為運用了兩階段式退火，可以有效的控制矽化鎳之側向成長至邊壁 (spacer) 之下方，避免了矽化鎳過度成長。(2) 而運用了離子植入矽化鎳技術可以避免了離子植入對通道矽之損傷，降低離子活化熱製程 (600oC, 30min)，有降低漏電流之優點。(3) 此外，修正矽化鎳之蕭基特位障(modified Schottky-barrier)源/汲極接面可提升元件之驅動電流(driving current)與降低漏電流之功效。 此外，我們也針對三閘極元件可靠度進行分析。發現當通道寬度(channel width) 縮小時，不但側向閘極 (side-gate) 電壓可以有效的降低通道電場與分散熱電荷之方向，較平整之矽化鎳前緣亦有改善元件可靠度之功用。而較深之側向閘極深度與較窄之通道寬度結構也可以遮蔽來自背閘極電壓之電場亦可有效降低底部氧化層 (buried oxide) 內部電荷與介面電荷對元件可靠度造成之影響。 其次，為了減少復晶矽空乏效應對元件特性退化之影響並簡化製程步驟。我們提出了新型全矽化鎳閘極修正蕭基特位障源/汲極覆晶矽元件(FUSI MSB FD-SOI)。此新型元件具有(1) 可消除復晶矽空乏效應。(2) 可同步利用低溫離子植入矽化鎳技術於源、汲、閘極工程。(3)運用離子植入矽化鎳技術不但可以改變了閘極之功函數(work function) ，同時可以與修正蕭基特位障源/汲極製程相容，以簡化製程步驟。對運用於未來之高速元件與高頻電路中相深具潛力。 接著，我們也驗證了低溫離子植入矽化鎳技術可以進一步運用於低溫複晶矽薄膜電晶體之源/汲極工程之製作。由製程角度觀之，低的熱運算可以增加產能；而由電特性角度觀之，可有效降低源/汲極寄生阻抗 (1.35K□-cm)並同時提升薄膜電晶體之開關電流比、開關速度、工作電壓、電子遷移率以及可靠度等特性。此外，優異的短通道特性 (Short channel effect) 更是適合應用於奈米級之低溫複晶矽薄膜電晶體。 最後，我們也製作出了一種新型的具低溫沈積之高介電常數介電層複晶矽薄膜電晶體 (HfO2 TFTs)。其運用了低溫成長(400oC)之氧化蛤薄膜(HfO2) 為閘極介電層，可以有效的降低了有效氧化層厚度 (EOT) 至7.3奈米。故與傳統之薄膜復晶矽電晶體相比較，其顯示較佳的元件電特性：開關電流比接近107，快速的開關特性 (S.S.~0.28V/Dec)、低閘極電壓 (0.3V) 等特性。與奈米等級通道寬度多閘極結構相結合應用後亦極適於運用於未來之面板上系統 (SOP)。

In this thesis, we studied the process technologies and device characteristics of novel SOI tri-gate FETs (TGFETs) and low-temperature poly-Si TFTs with NiSi films. Including thermal stability of NiSi films on different substrates, the control of lateral silicidation length by a two-step annealing method, applications of ITS technique on the S/D and gate electrodes of TGFETs were studied. Next, the impacts of channel width, side-gate depth, and back-gate bias on the device reliability were studied. Finally, to apply on the system-on-panel (SOP), poly-Si TFTs with modified Schottky-barrier (MSB) S/D junction and HfO2 gate dielectric layer were researched, respectively. First of all, we demonstrated that the NiSi films on the SiO2 substrate, without the excess Si atoms, have superior thermal stability. At the same time, using a special four-terminal sheet resistance test structure, the two-step annealing method was also found to well control the lateral silicidation length. Next, a novel 25nm modified-Schottky-barrier (MSB) SOI TGFET with NiSi S/D electrodes was fabricated by the low temperature two-step (300oC+600oC) NiSi silicidation and ITS technique. In this MSB TGFETs, low S/D external resistance, well-controlled NiSi profile, low temperature activation process, low S/D leakage current, and the high driving current owing to the MSB junction fabricated by ITS technique were also demonstrated. Besides, the reliability issues of TGFETs were also detail investigated. As the channel width reduces, not only the side-gate bias could effectively reduce the electric field in the channel and disperse the direction of hot-carriers, but the flatness of narrow silicide front-end was also another plausible reason that the device reliability could be enhanced. Moreover, deeper side-gate depth (DEXT) with narrower channel width structure was also demonstrated to shield the electric field from back-bias and then relaxed the influence of defects in the interface and bulk region of buried oxide. To solve the device performance degradation caused by poly-Si gate depletion effect while simplify the fabrication process, we also suggested the novel FUSI gate structure on the MSB FD-SOI devices by the same ITS technique. Using the ITS technique, the S/D and gate electrode could be fabricated easily at the same time. During this process, the poly-gate depletion could be suppressed; the work function could be suitable tuned. More important, this gate electrode engineering could be compatible with the fabrication process of MSB S/D junction. To conclude, these novel devices could be applied on high-speed device and radio-frequency circuits. In this thesis, we also illustrated the ITS technique on the fabrication of S/D electrodes of low-temperature poly-Si TFTs. For fabrication process, because of the low thermal budget, the throughput could be improved effectively. For electrical characteristics, smaller S/D parasitic resistance, larger Ion/Ioff current ratio, smaller subthreshold swing, smaller operation voltage, higher effective field mobility, and stable reliability were approached. Moreover, because of the superior short channel characteristics, the novel FSD TFTs were suggested to scale down to the nano-scale regime. Finally, a novel poly-Si TFT using a low-temperature and thin high-k (HfO2) film as gate dielectric was fabricated. In this device, the effective oxide thickness (EOT) could be scaled down to 7.3nm, and low gate leakage current could be maintained. The electrical characteristics including Ion/Ioff (~107), subthreshold swing (~0.28V/Dec), and threshold voltage (0.3V) were also approached. Combining the HfO2 gate dielectric with thin EOT and the ultra-narrow channel width structure, the novel HfO2 TFT was also verified to the future system-on-panel (SOP) applications.