銅製程中考量耦合電容與電鍍之無意義金屬擺放用以改善平整度

Abstract

晶片在新一代製程中，隨著特徵尺寸的縮小，在製造困難度及可靠度上相對遇到的困難也越來越多。這種情況下，使得必須要有更良好的晶片表面平整度才能改善晶片的性能和參數良率。普遍用來降低晶片表面地形變化的方法是在佈局上較空曠的區域中填入一些無意義的金屬，然而，這些填入的金屬會增加導線之間的電容因而造成延遲和耦合/串擾等雜訊問題。 在這篇論文中，我們提出了一個演算法特別去考慮到一些佈局上會影響電□表面的參數來做無意義金屬的填入，同時我們使用一個貪婪演算法來放置這些金屬，使得額外增加的耦合電容能達到最小。在實驗結果方面，我們與傳統上以佈局密度為主的演算法做比較，我們的方法在電鍍後厚度差和等效密度差上都能有顯著的改善，這表示對晶片表面的地形平整度能有明顯的改善。而且，我們放置無意義金屬的方法也能有效降低額外增加的耦合電容。

With feature sizes on chips shrinking at new process node, the difficulty in manufacturability and reliability of chips is increasing. It has necessitated better planarization of chip surface topography to improve both functional and parametric yield. The common solution to minimize topography variation is to insert dummy metals in empty spaces in the layout. However, these dummy metals will increase the capacitances between wires and then invoke delay and coupling/crosstalk noise problems. In this thesis, we propose an algorithm to consider especially the key layout parameters that affect the post-ECP (electroplating) topography and we use a greedy method to place the dummy metals with minimal additional coupling capacitances. Compared with a traditional density-based algorithm, the experimental result shows that our method has significant improvement on both post-ECP thickness variation and effective density variation which means the significant improvement in planarization of chip surface topography. Furthermore, our placing method of dummy metals can reduce the additional coupling capacitances efficiently.