IEEE 802.16e OFDMA通道編碼技術與數位訊號處理器實現之研究

Abstract

IEEE 802.16e 無線通訊標準中，於系統的傳送端訂定了前向誤差改正編碼的機制，藉此減低通訊頻道中雜訊失真的影響。通道編碼是本論文的重點。 本篇論文前半部份重點在於，研究IEEE 802.16e OFDMA所訂定的迴旋編碼系統並且實現在數位訊號處理器(DSP)上，針對DSP平台的特性以及迴旋編碼的演算法進行程式的改進。在論文中，我們將標準中制訂的四個必備的前向誤差改正編碼系統，利用C語言驗證我們整個系統演算法上的正確性，在加成性白色高斯通道下模擬了各種調變，模擬的結果增益比理論值大約有1dB的誤差，接著進一步以德州儀器公司所發展的TMS320C6416 DSP為核心的平台上實現。經過在DSP平台上最佳化我們的程式後，迴旋編碼的編碼器部份，於DSP模擬器上，可以到每秒13793K位元的處理速度，而解碼器的部份可以達到每秒805K位元的處理速度。 本論文後半部份重點，研究IEEE 802.16e OFDMA所訂定的低密度奇偶校驗碼系統並且實現在數位訊號處理器。研究低密度奇偶校驗碼傳統的編碼與解碼演算法，並且介紹一些降低解碼複雜度的演算法。用C語言驗證系統演算法上的正確性，在加成性白色高斯通道下模擬了各種調變與各種解碼演算法，並把模擬之結果與一些數學分析的結果做比較。模擬的結果顯示降低複雜度的演算法和傳統的解碼表現相當接近。接著從這些演算法中，根據運算複雜度，延遲時間，找出合適的演算法，實現在德州儀器公司所發展的DSP平台上。經過在DSP平台上最佳化我們的程式後，編碼器部份經過改進，可以到每秒835K位元的處理速度，而解碼器的部份僅可以達到每秒4.7K位元的處理速度。

In the IEEE 802.16e wireless communication standard, a Forward Error Correction (FEC) mechanism is presented at the transmitter side to reduce the noisy channel effect. The focus is on the channel coding. The focus of the fist part of this thesis is the research of the convolutional code defined in IEEE 802.16e OFDMA standard and modifying FEC algorithms to match the architecture of DSP platform. We have implemented four required FEC schemes defined in the standard on the C program to insure the correctness of our algorithm. We simulate the different modulation in AWGN channel and the coding gain is almost achieve theoretic values. Then we implement the project on the Texas Instruments digital signal processor (DSP). After optimizing the programs on the DSP platform, the improved FEC encoder can achieve a data processing rate of 13793 kbps and the improved FEC decoder can achieve a processing rate of 805 kbps on the TI TMS320C6416 DSP simulator. The focus of second part is the low-density parity-check (LDPC) code defined in IEEE 802.16e OFDMA. We explain the conventional encoding and decoding algorithm, and some reduced-complexity decoding algorithms. We simulate the LDPC code for different modulation and decoding algorithms in AWGN and compare the simulation results with analytical results. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of conventional algorithm. According to computational complexity and latency, we choose the adaptable algorithm and implement on DSP. After optimizing the programs on the DSP platform, the improved encoder can achieve a data processing rate of 835 kbps and the improved decoder can achieve a processing rate of 4.7 kbps on the TI C6416 DSP simulator.