薄膜電晶體主動式矩陣面板之陣列技術研究

Abstract

本論文首先提出一種具有高導通電流的新穎非晶矽薄膜電晶體元件結構。將Akiyama所提出之遮光結構(light-shield)結構改善，利用多一次重□雜的非晶矽(n+ a-Si)沉積的引入，將縮於閘極內的非晶矽主動區包圍起來，可以有效阻止金屬與本質非晶矽的接觸，所以光漏電流與暗漏電流皆有明顯改善；此外由於比傳統BCE 結構多了側壁導通區，使得部份載子可以直接透過側壁進出，有效降低汲/源極寄生電阻，使得整體新結構非晶矽元件導通能力上升，比相同製程之傳統BCE結構提升了50%的導通能力，載子遷移率可達1.05 cm2/Vsec，新結構元件可應用於大尺寸電視所需之高導通能力畫素開關元件或是用來驅動有機發光二極體(OLED)。 此外，由於多晶矽薄膜電晶體能夠整合週邊驅動電路進而由於多晶矽元件應用於面板週邊驅動邏輯電路時，需要考量到多晶矽元件可靠度的問題，本論文針對多晶矽元件在AC gate bias stress之後的劣化機制做一深入探討，研究中發現AC gate bias stress 會造成元件導通電流嚴重的下降，但其起始電壓變化並不大，根據Seto理論，我們計算出元件劣化前後其有效缺陷密度(effective trap density)，由原本的1.42×1012cm-2增加至3.14×1012cm-2，並且由其劣化趨勢推論這些缺陷大部分屬於tail states，同時汲/源極寄生電阻的也急劇增加；藉由在較高的源極電壓下操作使元件在saturation region (Vds>Vgs)並且有pinch-off region在汲極附近產生，可以發現導通電流劣化的程度縮小，故可以判定劣化區域是靠近汲/源極，因為在pinch-off region中，載子不再限定於通道表面傳輸而是可以透過bulk方式傳輸，若是AC stress產生的大量tail states位於汲極附近的通道表面，當pinch-off region 在汲極附近產生，載子便可避開這些高電阻區而透過bulk傳輸到汲極，故其導電特性與會隨汲極端電場而有所變化。 本論文也研究探討多晶矽薄膜電晶體元件的溫度效應，首先對non-LDD的薄膜電晶體做研究，實驗發現non-LDD的元件會隨著溫度下降而導通電流增大，主要原因是因為聲子散射(phonon scattering)的緣故，聲子主要是源由晶格熱震動所產生，聲子會隨著溫度上升而增加，溫度下降而減少，若載子與聲子間的碰撞越多其自由路徑會越短，載子遷移率也會隨之下降。然而在LDD元件中，元件導電率與溫度成正比，溫度越高導電率越高，LDD元件與溫度關係與non-LDD元件逕相庭徑，為了釐清兩者之差別，本論文觀察N+ 與N- 的片電阻率隨溫度的關係，然而N-電阻率隨著溫度上升而嚴重下降，N+ 則較不受溫度變化影響，由於N-中摻雜濃度並非達到使多晶矽導電程度達到簡併態，其自由載子濃度為有效摻雜濃度扣除缺陷態位密度，而隨著溫度下降而參雜活化比率下降，所以N-阻值上升，故LDD電阻特性對於元件溫度效應中扮演一重要角色，為確保在適當溫度範圍內面板能正常工作，這些元件的溫度函數是未來電路或是面板設計上一大考量。 本論文中有探討新型側向結晶方式Sequential Lateral Solidification (SLS)所製作出的多晶矽元件其電性與可靠度，由材料分析上可發現SLS所產出的晶粒尺寸比一般傳統excimer雷射來得大，我們可以將SLS晶界分為二種：一為主晶界(main-GB)，二為次晶界(sub-GB)，主晶界的特徵在於其晶界走向垂直元件通道方向，並且在多晶矽薄膜結構中為一突起(protrusion)；次晶界則是平行通道方向且較平坦，論文中挑選兩種較明顯對比之電晶體進行分析，GB-TFT為一含有主晶界在通道中央，NBG-TFT中則僅有次晶界存在，由電晶體參數萃取可發現NGB-TFT其起始電壓、次臨界撥動、載子遷移率都比GB-TFT優良；然而在hot carrier stress實驗中則是GB-TFT展現較高的可靠度，透過模擬軟體的計算分析可發現由於GB-TFT通道中央存在有主晶界的存在，這個高缺陷密度的區域能有效降低汲極端電場，進而降低了hot carrier effect。 本論文也研究兩種poly-Si EEPROM元件結構，一為floating gate為儲存電荷單元，另一為SiN為電荷儲存層。本論文首先提出新的doping方式來改善floating gate EEPROM的閘極電壓耦合效果，可以降低記憶寫入電壓，或是擁有較快的寫入速度，而且元件導通電流也被提昇了；此外利用Oxide/Nitride/Oxide的堆疊，可以在玻璃上製作EEPROM元件而達到與晶圓上MONOS的記憶效果，實驗中的穿邃氧化層厚度為15nm，氮化矽為15nm，Block oxide為25nm，本論文也發現利用F-N tunneling寫入抹除的方式，比較不會破壞多晶矽記憶體元件的特性，若是以Channel hot carrier方式的話會造成元件開關特性的劣化，起始電壓的飄移，這是由於多晶矽的閘極氧化層為低溫沉積，其品質較晶圓熱氧化層差，而且熱載子效應會因為玻璃絕緣基板的floating body effect而更嚴重，會使得多晶矽元件閘極氧化層容易劣化。 本論文最後研究具有低RC延遲之連線技術，相似於IC的多層導體連線技術發展，Cu導線與low-k材料將是最佳的選擇。本論文先就一種多孔隙的low-k材料進行基本特性研究，量測其介電常數並觀察漏電流等等，由於多孔隙材料其孔隙度高，表面積也相對來得大，容易造成水氣吸附在表面並造成的介電特性改變。此外，銅金屬與low-k材料的整合會面臨到銅金屬擴散造成low-k材料劣化，論文中就水氣造成銅金屬擴散問題作一深入分析，實驗發現水氣會使銅離子更容易在高電場驅策下而進入low-k中。而為了避免銅金屬擴散問題，可以引入介電阻障層來隔絕銅金屬與low-k直接接觸，研究中探討了SiCN絕緣薄膜對阻擋銅擴散的能力的表現，觀察不同氮含量的材料組成對於阻障能力的影響，最後本論文也提出一個SiCN阻障層漏電流劣化的物理模型。

A novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) TFT is first developed in this thesis. In the bottom gate light-shield a-Si:H TFT structure, the side edge of a-Si:H island is capped with an extra deposition of heavily phosphorous-doped a-Si layer. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts between source/drain metal and a-Si:H at the edge of a-Si:H island. In addition, our proposed a-Si:H TFT device exhibits superior effective carrier mobility, as high as 1.05 cm2/Vsec due to the enormous improvement in parasitic resistance. We have evidenced that the leakage current of proposed TFT is lower than the conventional BCE device under bottom-side illumination of 6000 nits. It also exhibits the better ability against the DC current stressing. The impressively high performance provides the potential of the proposed a-Si:H TFT to apply for AMLCD and AMOLED technology. Next, the temperature and AC gate pulse stress effects on ELA poly-Si TFT have been demonstrated. We find that the conducting current of non-LDD poly-Si TFT is increasing with the decreasing in the temperatures. The phonon scattering is responsible for the evolution of carrier mobility in poly-Si TFT at temperatures. However, the LDD poly-Si TFT is obviously influenced by the LDD layers extended outside the gate electrode. LDD sheet works as a larger resistor at low temperature than that at high temperature. These results can provide the designers to consider the temperature effects for the poly-Si TFT application in a suitable temperature range. In addition, the distinct decrease in ON-current of n-channel poly-Si TFT was found during the dynamic voltage stress. In spite of electrical degradation appearing at the ON-current of the poly-Si TFT, both the sub-threshold swing and threshold voltage kept in a good condition. This can be inferred that the tail states were produced in ploy-Si film due to the AC stress. Additionally, the current crowding effect was increased with the increasing of stress time. The parasitic resistances extracted from the ID-VD curves of poly-Si TFTs were significantly increased after the 1000 s stressing. The effective trap density of poly-Si TFTs stressed for 1000 s was 3.14×1012 cm-2, 2.21 times larger than that of the un-stressed device. The creation of effective trap density in tail-states is responsible for the raise of the parasitic resistance and the degradation in ON-current of TFT. Moreover, the damaged regions whicn contains numerous trap states are evidenced to be mainly located near the source /drain regions. On study the grain –boundary (GB) effects, the comparison of electrical stability between GB and NGB-TFT has been demonstrated. The NGB-TFT owns superior conducting ability than the GB TFT which contains a 100-nm trap-numerous region at the middle of the channel. However, the GB-TFT exhibits the better endurance against DC stress than the NGB-TFT. Based on the simulation result, the existence of GB in the middle of channel of poly-Si TFT would reduce the electric field in the drain region significantly. Accordingly, the GB-TFT suffers relatively lighter impact of hot carrier stress and maintains electrical characteristics well during the DC stressing. The NGB-TFT was seriously degraded by the DC stress with the high electric field at the drain side. Nevertheless, the distinct electrical behaviors of the TFTs were demonstrated under the AC gate bias stress. Due to the existence of protrusion in the channel, GB-TFT shows weaker endurance against the AC gate pulse stress than that of NGB TFT. The magnitude of the vertical field at the protrusion is stronger than the other regions in GB TFT. The strong electric field would lead to the state creation and charge trapping at the protrusion and reduce the device’s electrical performance. On the study of non-volatile memory devices fabricated on glass using low temperature poly-Si technology, two structures have been fabricated and characterized. One is floating-gate device and the other consists of the oxide-nitride-oxide stack structure. The maximum temperature of processing is below 650oC for the glass substrate. The floating-gate memory device consists of two active regions of poly-Si layer, one behaves as the control gate and the other is the conducting channel region. The control-gate transistor of the device is proposed to consist of a whole heavily-doped poly-Si sheet. The higher coupled efficiency of gate bias is demonstrated in the proposed structure. Also, the characterizations of MONOS type memory with an oxide-nitride-oxide (ONO) stack structure were studied. In comparison with channel hot carrier injection, the Fowler-Nordheim tunneling method is more suitable for the programming of the poly-Si memory device. The memory widow of devices can reach 1.5V under the programming voltage of 20V for 10ms. The device maintains a wide threshold voltage window of 1.5V after 104 program/erase cycles. Moreover, it retains a good retention property without a significant decline of the memory window up to 50 hours at 60oC. On the study of interconnections with low-RC delay, the porous organosilicate glass (POSG) and a-SiCN have been investigated. The lager leakage current is observed in hot-water dipped POSG sample. The leakage current would be increased and dominated by the ionic conduction as the moisture is contained in the POSG. Additionally, the moisture would enhance the Cu to penetrate into POSG and cause the raise of the leakage current. To avoid the Cu contamination in the interconnections, the electrical properties and stabilities of barrier dielectric a-SiCN films are investigated. The leaky behavior of a-SiCN is evidenced to be Pool-Frenkel conduction in high electric field region. Experimental results indicate that a-SiCN films containing higher nitrogen concentration exhibits better barrier ability. The dielectric breakdown is due to the penetration of Cu. It is observed that the main conduction of post-breakdown a-SiCN at room temperature (298K) is space-charge-limited current (SCLC) due to numerous Cu impurity/traps. Moreover, the characteristics at low temperature can be separated into two distinct stages, Fowler–Nordheim tunneling and space-charge-limited current (SCLC) conduction. We propose a physical model which post-breakdown a-SiCN was composed of two different conduction regions. It can well describe the electrical variation resulted from the Cu traps and temperature.