IEEE 802.16e OFDMA同步技術之研究與數位訊號處理器實現

Abstract

本篇論文介紹IEEE 802.16e正交分頻多工存取(OFDMA)裡，同步的問題、演算法、以及實做方面的議題。 當一個行動電話在一開始要進入網路的時候，我們必須做起始的同步。在起始的同步中，包含了符碼時間偏移、載波偏移和前置符元序號(preamble index)需要同步。我們使用循環字首(cyclic prefix)的相關性(correlation)及在第一個下行次訊框(subframe)裡的資訊來估計出較準確的符碼時間偏移和小數部分載波偏移。之後我們在頻域上用補償之後的同步碼來聯合估計出整數載波偏移和前置符元序號。我們利用前置符元序列和前置符元的特性來做估計，另外我們也介紹了一些不同複雜度的方法。 在之後的次訊框中，行動電話只需要做到追蹤符碼時間偏移和小數部分載波偏移。我們再次使用循環字首的相關性並在每個符元間利用指數平均來求得較準確的結果。另外，因為我們在非起始的同步中，我們已經知道前置符元序號，因此我們可利用這個資訊來估計符碼時間偏移。這個方法主要是利用前置符元序列之間的準正交性的特性來估計。我們首先是用浮點數運算來驗證，並同時在可加性白色高斯雜訊通道(AWGN)以及多路徑Rayleigh衰減通道下做模擬，模擬速度高達120 km/h，並觀察其結果。 最後，我們把這些方法修改成定點運算的版本，並在數位訊號處理平台上，最佳化我們的程式的速度。雖然修改成定點運算會使效能衰減，但其結果依然可以接受。經過最佳化之後，同步的工作都能達到即時處理(real time)的要求。

This thesis introduces the synchronization problems, algorithms, and imple- mentation issues of IEEE 802.16e OFDMA system. In DL synchronization, the (mobile station) MS receiver needs to perform initial synchronization upon its initial entrance to the network. There are timing offset, carrier frequency offset (CFO), and preamble index needed to be estimated during initial synchronization. We use the information of the first DL subframe to estimate the more accurate timing and fractional CFO by cyclic prefix (CP) correlation. Then, we consider the joint detection of integer CFO and preamble index using the compensated preamble in the frequency domain. The preamble sequences and the feature of preamble symbol are exploited and a number of detection methods of different complexity are introduced. In subsequent subframe, the MS only needs to track the timing offset and fractional CFO. We use CP correlation with exponential average over the symbols in the subframe to obtain a more accurate estimation. Besides, we also afford a data-aided method to estimate the symbol timing since we already know the preamble index during normal synchronization. This method exploits the quasi-orthogonality among the preamble sequences. We verify our system in floating-point computation, and simulate our system in both AWGN and multipath Rayleigh fading channel, which the speed is as high as 120 km/h, and see the performance. In the end, we modified these methods into fixed-point version, and then optimize the speed of our programs on the digital signal processor (DSP) platform. Although the performance is degraded because of fixed-point modification, the results still can be accepted. After DSP optimization, the synchronization tasks can achieve the real-time requirement.