射頻互補金氧半E類功率放大器設計

Abstract

本文提出一個完全整合在單一晶片上使用0.13-μm CMOS製程的E類功率放大器，此E類功率放大器結合了F類的前級放大器並採用有限的小面積電感來取代大面積的射頻阻隔器以易於整合在單一晶片上。此E類放大器在輸入功率為-3dBm、操作頻率為2.5GHz之下，可達到21dBm的輸出功率和48.4%的功率增加效率，在設計的頻帶內，2.3GHz~2.7GHz，功率增加效率仍然可以維持在44%以上。且為了增加系統模擬的時間，本文提出此E類功率放大器的形為模型。藉由此形為模型，系統模擬的時間可以減少93%左右。

An on-chip CMOS Class-E Power Amplifier (PA) implemented in 0.13-□m CMOS technology is presented. The Class-E PA includes a Class-F driver and replaces a large RF choke with a small finite dc-feed inductor for on-chip integration. The proposed Class-E PA achieves power added efficiency (PAE) of 48.4 % while delivering 21 dBm output power with the input driving power of -3 dBm at 2.5 GHz. In the design band, 2.3GHz~2.7GHz, PAE is still above 44%. In order to improve the simulation time of RF/Baseband co-simulation the behavior model of proposed PA is presented. The simulation time of RF/Baseband co-simulation can be reduced about 93% by the proposed behavior model.