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DC Field | Value | Language |
---|---|---|
dc.contributor.author | 王依翎 | en_US |
dc.contributor.author | Yi-Ling Wang | en_US |
dc.contributor.author | 林大衛 | en_US |
dc.contributor.author | David W. Lin | en_US |
dc.date.accessioned | 2014-12-12T03:03:02Z | - |
dc.date.available | 2014-12-12T03:03:02Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009411671 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/80585 | - |
dc.description.abstract | 正交分頻多重進接(OFDMA)技術近來在行動環境中廣受注目且已經應用在許多數位通訊應用中。採用OFDMA一個最主要的原因是其抗頻率選擇性衰變及窄頻干擾的能力。我們聚焦在IEEE 802.16e OFDMA上行及下行傳輸的通道估測部分。我們並在Sundance公司的版上裝置德州儀器公司的TMS320C6416數位信號處理器來實現通道估測的機制。 通道估測大致可以分成三個階段。首先我們使用最小平方差的估測器來估計在導訊上的通道頻率響應,這是為了硬體的計算方便。其次我們在頻率域上使用線性內插法來得到在資料載波上的通道響應。最後我們使用平均時間技巧在時域上來增進其效能。我們先在AWGN通道上驗證我們的模擬模型,然後再放置於多重路徑的SUI-2和SUI-3通道上模擬。 在上行傳輸,我們提出了瓦線性內插法;而在下行傳輸,我們有提出了2點、4點以及進階4點群線性內插法。為了增進程式在數位訊號處理器上的執行效率,我們先將原始的浮點運算C程式版本修改為實數運算的程式版本,接著再考慮數位訊號處理器的特性來修改之前的程式 在本篇論文中,我們首先簡介IEEE 802.16e OFDMA上行及下行的標準機制和DSP的實現環境。接著,我們分別在各傳輸情形下介紹所用的通道估測方法並探討其估測效能及數位訊號處理器實現方面的實驗結果。 | zh_TW |
dc.description.abstract | OFDMA (orthogonal frequency division multiple access) technique has drawn much interest recently in the mobile transmission environment and been successfully applied to a wide variety of digital communications applications over the past several years. One of the main reason to use OFDMA is its robustness against frequency selective fading and narrowband interference. We focus on the OFDMA uplink and downlink channel estimation based on IEEE 802.16e. We also implement these channel estimation schemes on Texas Instruments’ TMS320C6416 digital signal processor (DSP) housed on Sundance board. The channel estimation schemes can be separated into three steps. First, we use LS estimator on pilot subcarriers because of its low computational complexity. Second, we estimate the channel response on data subcarriers using linear interpolation in the frequency domain. Finally we try time averaging technique to improve the performance in the time domain. We verify our simulation model on AWGN channel and then do the simulation on SUI-2 and SUI-3 multipath channels. In uplink transmission, we propose the tile linear interpolation and as for downlink, we use the 2-point, 4-point and advanced 4-point cluster linear interpolation. In order to increase the efficiency on DSP, we rewrite the floating-point C program to fixed-point version and further refine our codes by considering the features of the DSP chip. In this thesis, we first introduce the standard of the IEEE 802.16e OFDMA uplink and downlink and the DSP implementation environment . Then we describe the channel estimation methods we use and discuss the performance and the DSP implementation results in each transmission condition. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 通道估測 | zh_TW |
dc.subject | Channel Estimation | en_US |
dc.subject | 802.16e | en_US |
dc.title | IEEE 802.16e OFDMA 上行及下行通道估測技術之探討與數位訊號處理器實現 | zh_TW |
dc.title | Research in and DSP Implementation of Channel Estimation Techniques for IEEE 802.16e OFDMA Uplink and Downlink | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
Appears in Collections: | Thesis |
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