掃描鏈重新排列減少掃描移動功率架構在非指定的測試集合

Abstract

這篇論文提出掃描元件的重新排列架構在非指定的測試集合， 能保留測試圖案中不在乎位元的值用來減少在測試模式下所產生的 信號變動量。首先，我們提出以掃描元件反應值之間的關係性來引導 重新排列，並且用填值技術來減少掃描進的信號變動。接下來我們提 出同時考慮掃描元件反應值和測試圖案之間的關係性來幫助排列並 且同時減少掃描進和出的信號變動。一個反向的技術應用在此方法上 進一步減少測試功率。除了功率導向的重新排列技術，我們最後提出 同時考慮功率和繞線的方法，在兩者間做取捨以達到減少違背時間限 制的情況發生。最後，我們做一些實驗來論證提出方法的有效性和優 勢關於在減少掃描移動時所產生的信號變動。此外，關於同時考慮功 率和繞線的情況也透過實驗來做討論。

This thesis proposes a scan-cell reordering scheme based on unspecified test vectors to reduce the signal transitions during test mode while preserving the don’t-care bits in the test patterns for a later optimization. First, we introduce a method that uses response correlations to guide the scan cell reordering and specify don’t care bits through a pattern-filling technique to reduce scan-in transitions. Next, a proposed scheme utilizes both response correlation and pattern correlation to simultaneously minimize scan-out and scan-in transitions. A extension of the scheme that reverse-combined technique applied to the method further reduces test power. Except power-driven scan cell reordering methodology, we last propose a methodology that takes the routing overhead into consideration and derive a new ordering methodology based on power and routing concerns. We can make a tradeoff between power and routing to reduce timing violations. A series of experiments demonstrate the effectiveness and superiority of the proposed scheme on reducing total scan-shift transitions. The effectiveness of the scheme considering both power and routing overhead is discussed through experiments as well.