電漿製程導致先進互補式金氧半場效電晶體可靠度損壞之研究

Abstract

本論文對於先進互補式金氧半場效電晶體技術中，電漿製程導致可靠度上的損壞發表其描述模型和特性分析。其中藉由天線效應測試鍵載具的設計，包含超薄氧化層複晶閘電晶體，高介電層金屬閘(High-k/Metal-gate)電晶體，絕緣層上矽 (SOI)電晶體，金屬絕緣層金屬電容器(MIM)等先進互補式金氧半場效電晶體元件的製作， 以及多種可靠度上影響的評估，如閘極介電層失效，介電層依時崩潰特性(time dependent dielectric breakdown，TDDB)， 負偏壓溫度不穩定性(negative bias temperature instability，NBTI)，正偏壓溫度不穩定性(positive bias temperature instability，PBTI)和熱載子注入(hot carrier injection，HCI)效應等。電漿製程引起元件可靠度的不穩定性，對積體電路的生產是非常重要的，而我們提出的描述模型可用於決定電路中可容許的天線比 (Antenna Ratio，AR) ，並預估電路中介電層和電晶體可靠度的劣化程度。 首先, 針對氧化層複晶閘電晶體，電漿製程對其氧化層和電晶體可靠度的損壞加以探討。對於天線效應，氧化層穿隧，氧化層面積，氧化層厚度等因素增加電漿製程損壞，造成閘極電流上升，和負偏壓溫度不穩定性的特性，建立一個可預估模型。我們描述天線效應造成介電層依時崩潰特性的劣化現象，包含平均生命期失效(mean time to failure，MTTF)退化，和偉伯分佈曲線上斜率衰減。我們也提出氧化層失效率和天線效應之間的關係。而我們建立的電晶體可靠度退化的模型，可以適用於預估P型金氧半場效電晶體在負偏壓溫度不穩定性上的失效分佈。 其次，我們研究電漿製程對高介電層金屬閘電晶體的損壞，並和氧化層複晶閘電晶體針對電漿製程導致元件可靠度劣化程度作一比較。我們發現在相同的介電層物理厚度情況下，高介電層金屬閘電晶體的損壞程度較低。除了介電層的劣化現象，這些研究更深入探討電晶體可靠度衰減的問題，包含N型金氧半場效電晶體在正偏壓溫度不穩定性，和P型金氧半場效電晶體在負偏壓溫度不穩定性等特性。這些電晶體可靠度的不穩定特性是由於電漿製程導致氧空缺(Oxygen Vacancies)的產生，進而在可靠度實驗加高電壓量測時補捉電子。當縮減介電層的等效氧化層厚度(equivalent oxide thickness，EOT)， 可減少電漿製程對介電層和電晶體的損壞程度。 再則，對於研究電漿製程對金屬絕緣層金屬電容器的損壞，我們針對下接式(Tie-Down)金屬絕緣層金屬電容器和浮動式(Floating)金屬絕緣層金屬電容器提出描述模型。藉由在電容的上極板接上大面積的內連接線，明顯看出下接式金屬絕緣層金屬電容器比浮動式金屬絕緣層金屬電容器較容易受到電漿製程的損壞。另外，亦針對上接式(Tied-Up)電晶體的閘極連到有高天線率的上極板(ARCTM)之金屬絕緣層金屬電容器，或是有高天線率的電感(ARInductor)之電漿製程損壞程度作一討論。研究發現電晶體可靠度的劣化和上極板的天線率及電感的天線率有相關。並且證實氧化層厚度為 3.0-5.0 nm時，是比厚度為 1.5 nm時的上接式電晶體更容易受到電漿製程的損害。 最後，我們討論絕緣層上矽(SOI)電晶體可靠度的電漿製程損壞害機制和描述模型。我們針對P型金氧半場效電晶體的可靠度，在有同樣的複晶閘天線效應下，研究因電漿製程損壞害產生對負偏壓溫度不穩定性特性，結果發現絕緣層上矽電晶體比矽基板電晶體不易受到電漿製程影響。並且，我們也調查N型矽晶絕緣金氧半場效電晶體的可靠度，發現在同時有汲極和閘極天線效應下，電漿製程會對於氧化層和電晶體熱載子注入等相關可靠度進行破壞。進一步，我們發現N型矽晶絕緣金氧半場效電晶體可靠度衰減的機制是因為在製程過程中，汲極和閘極同時受電漿製程損壞引起的熱載子注入效應，而產生的介面陷井是分佈在通道的中心至汲極端。

This dissertation presents the modeling and characterization of plasma induced damage (PID) on the reliability of advanced complementary metal-oxide- semiconductor (CMOS) technology. We designed antenna test vehicles, fabricated advanced CMOS devices involving ultra–thin SiO2/poly-gate transistors, high-k/metal-gate transistors, silicon-on-insulator (SOI) transistors, metal-insulator- metal (MIM) capacitors, and further evaluated their reliabilities including gate dielectric failure, time dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI) reliability. These reliability instabilities caused by plasma damage is very important for integrated circuit manufacturing. Moreover, our proposed models can be applied to choosing the maximum antenna ratio (AR) and predicting the dielectric and transistor reliability degradations in the circuit. First, plasma damage on oxide and transistor reliability in SiO2/poly-gate MOSFETs were investigated. The prediction models of damage-enhanced gate leakage and NBTI lifetime degradation as a function of antenna effects, gate oxide area, oxide tunneling, and gate oxide thickness were established. We then presented the antenna effect on TDDB degradation in terms of mean time to failure (MTTF) and Weibull slope (β). We observed a relationship between antenna effect and gate oxide failure fraction. We further demonstrated that the transistor reliability degradation model can be used to predict the failure distribution for PMOSFETs’ NBTI reliability. Second, we demonstrated damage impact in high-k/metal-gate transistor reliability and compared the damage-enhanced degradations between high-k/metal-gate and SiO2/poly-gate transistors. We found that the high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with the same physical dielectric thickness of approximately 3.0-4.0 nm. In addition to dielectric degradation, this study investigated transistor reliability issues, including NMOSFETs’ PBTI and PMOSFETs’ NBTI by damage-enhanced generation in oxygen-vacancy-related defects, and electron captured in oxygen vacancies during reliability testing. We found that reducing the equivalent oxide thickness (EOT) suppresses the gate dielectric and transistor degradations caused by plasma damage. Next, we studied the plasma damage in MIM capacitors, we established a damage model for tied-down MIM capacitors and floating MIM capacitors, respectively. It is evident that tied-down MIM capacitors show significant plasma damage by the capacitor-top-metal (CTM) connecting to large interconnects. Furthermore, the damage on tied-up transistors with their gates connecting to MIM with a large ARCTM or spiral inductor with large ARinsulator was discussed. We found that the reliability degradations of these transistors are functionally dependent on ARCTM and ARinductor, and transistors with a thick gate oxide of 3.0-5.0 nm are more susceptible to plasma damage than those with a thin oxide of 1.5 nm. Finally, we demonstrated the damage mechanism and models on SOI transistor reliability degradation. We showed that the SOI MOSFETs depict less damage impacts on NBTI of PMOSFETs with poly antenna, as compared with Si-bulk transistors. Furthermore, we studied that damage impacts on oxide degradation and HCI reliability of the NMOSFETs connected both with large drain antenna and gate antenna. We further discovered the damage mechanism as damage-enhanced hot carrier effect and the trap generation distributed from the center to the drain side for SOI MOSFETs under drain and gate damage.