标题: 全金属矽化物互补式金氧半制程之矽控整流器及其在射频电路之静电放电防护设计与应用
SCR-Based ESD Protection Designs for Radio-Frequency Integrated Circuits in Fully Silicided CMOS Process
作者: 林群佑
Lin, Chun-Yu
柯明道
Ker, Ming-Dou
电子研究所
关键字: 静电放电防护设计;矽控整流器;射频积体电路;ESD Protection Design;Silicon-Controlled Rectifier;Radio-Frequency Integrated Circuit
公开日期: 2008
摘要:   在所有积体电路产品中,皆必须于量产时符合可靠度 (Reliability) 的规范,以提供该积体电路产品足够的耐用年限。而随着奈米级互补式金氧半制程的持续发展,静电放电 (Electrostatic Discharge, ESD) 防护已成为积体电路产品可靠度中相当艰钜的挑战,大多数电子产品的故障与损坏均与遭受静电放电轰击有关。为避免积体电路遭受静电放电的威胁与破坏,所有积体电路与外界接触的焊垫 (Pad) 皆须搭配静电放电防护设计。
  无线通讯装置中的射频 (Radio Frequency, RF) 电路,因其连接射频收发机与外接之滤波器或天线,因此亦需搭配静电放电防护设计。由于射频电路操作在数十亿赫兹 (Gigahertz, GHz) 以上的工作频率,如此高频的工作频率对于讯号路径上的寄生效应有极为极严格的限制,静电放电防护电路的寄生效应必须达到最小化的设计,以避免射频电路性能的严重衰减。在寄生效应严格限制的情况下,矽控整流器 (Silicon-Controlled Rectifier, SCR) 是极为有用的静电放电防护元件。由于在二极体 (Diode)、矽控整流器、双载子电晶体 (BJT)、金氧半场效电晶体 (MOSFET)、或者是场氧化层电晶体 (Field Oxide Device, FOD) 等众多的静电放电防护元件中,矽控整流器具有面积最小、寄生效应最小、静电放电耐受度最好的优点,并且完全相容于一般互补式金氧半制程的步骤,不需额外的光罩去遮蔽金属矽化物 (Silicide Blocking),尤其将它应用在先进制程中不会有闩锁效应 (Latchup) 的问题,因此可以广泛应用在积体电路中当作静电放电防护元件。然而过高的触发电压与较慢的导通速度,使得矽控整流器在实际应用上必须搭配有效地低电压触发与高效率导通之设计。矽控整流器基本特性是由电流触发而导通的元件,所以当有一触发电流施加于矽控整流器的基体时,矽控整流器便可很快地经由正回授再生机制 (Positive-Feedback Regeneration Mechanism) 触发进入导通状态。
  搭配矽控整流器的射频电路之静电放电防护设计是本论文的研究主题,本论文的章节包括:(1) 使用交叉耦合 (Cross Couple) 的矽控整流器之差动式低杂讯放大器 (Low-Noise Amplifier, LNA) 设计、(2) 超低寄生电容的矽控整流器设计、(3) 搭配超低寄生电容的矽控整流器之超宽频功率放大器 (Power Amplifier, PA)、(4) 应用在射频电路与静电放电防护电路共同设计之寄生电容模型、(5) 利用矽控整流器设计之可耐高工作电压以及低漏电之静电放电箝制电路。
  本论文第二章针对一种射频窄频前端电路与静电放电防护电路共同设计。本章使用 130 奈米互补式金氧半制程设计一个工作于 5 GHz 的差动式低杂讯放大器,并探讨差动式低杂讯放大器接点对接点 (Pin to Pin) 之静电放电耐受度。新提出的静电放电防护设计于两个差动输入焊垫间使用交叉耦合的矽控整流器,除了可提供单一输入焊垫至电源线与接地线的静电放电防护外,更可提供两个差动输入焊垫间的接点对接点模式静电放电防护功能。此设计的人体放电模式 (Human Body Model, HBM) 与机械放电模式 (Machine-Model, MM) 静电放电耐受度分别为 3.5 kV 与 300 V。相关的射频性能以及静电放电耐受度皆于第二章内比较与讨论。
  第三章藉由改变矽控整流器的元件布局方式以降低寄生效应。在矽控整流器中使用方块状 (Waffle) 之新型布局结构,可在相同晶片布局面积下提供最大静电放电路径周长,因此可在最小寄生电容的前提下,提供最高的静电放电防护能力。换句话说,方块状之矽控整流器可降低元件本身的寄生电容值。本研究于 0.18 微米互补式金氧半制程中实现此新型设计,并且不需增加元件和其他成本,故十分适合应用于射频电路之静电放电防护设计。
  利用新提出之方块状矽控整流器,第四章将其应用于射频功率放大器之静电放电防护电路。本章使用 130 奈米互补式金氧半制程实现此射频电路,实验证明此静电放电防护策略可有效地提供防护等级超过 8-kV 人体放电模式之静电放电轰击测试、与 800-V 机械放电模式之静电放电轰击测试。实验结果亦证明,静电放电轰击确实对射频功率放大器的射频操作效能有极大的影响,射频功率放大器极需静电放电防护设计,否则无法于静电放电轰击下存活。
  随着射频电路工作频率持续升高,静电放电防护电路的寄生效应也愈来愈难以掌握,因此,需要将电路中所使用的元件模型建立起来,才能更有效地控制静电放电防护电路的寄生特性。本论文第五章建立起矽控整流器在高频操作时的元件模型,以便利用射频电路与静电放电防护电路共同设计的方式,设计出具有良好射频效能以及优异静电放电防护能力的射频积体电路。除了静电放电防护元件以外,焊垫也会在讯号路径上对射频讯号造成负面影响。本章针对一种具有低电容值的焊垫进行研究,利用其等效电路模型进一步提出低损耗 (Loss) 设计,并于 65 奈米互补式金氧半制程中实现此设计。实验结果显示,焊垫的等效电容可于特定频段内大幅降低,同时讯号损耗也可降低,因此可避免影响射频电路之性能。
  电源箝制静电放电防护电路 (Power-Rail ESD Clamp Circuit) 是达成积体电路产品全晶片静电放电防护极为重要的设计,本论文第六章提出了新型的可耐高工作电压以及低漏电之静电放电箝制电路。本章使用 65 奈米互补式金氧半制程实作,在此可耐高工作电压之静电放电箝制电路中,所有电晶体都是利用低压元件来实现,可以安全地偏压在两倍工作电压下而不会有闸极氧化层的可靠度问题,并且不需使用低漏电制程即可达成降低漏电的目标。由实验结果可知,此电路拥有极高的静电放电能力,而且在正常操作的情况下只有 100-nA 等级的漏电流,因此,本静电放电箝制电路十分适合应用在系统单晶片 (System-on-a-Chip, SoC) 之混合电压输入输出界面 (Mixed-Voltage I/O Interfaces)。
  第七章总结本论文的研究成果,并提出数个接续本论文研究方向的研究题目。本论文所提出的各项新型设计,皆已搭配实验晶片加以验证。此外,本研究有数篇国际期刊与国际研讨会论文发表,并有数项创新设计已提出中华民国及美国专利申请。
In order to be safely used and provide moderate life time, all microelectronic products must meet the reliability specifications during mass production. Electrostatic discharge (ESD), which was one of the most important reliability issues in the integrated circuit (IC), must be taken into consideration during the design phase of all IC products. All pads which connect the IC and the external world, including the input/output (I/O) pads, VDD pads, and VSS pads, need to be equipped with ESD protection circuits to provide effective ESD protection for the IC. Since the radio-frequency (RF) front-end circuits in wireless communication devices connect the RF transceiver to the external antenna or band-select filter, they must need ESD protections. However, the ESD protection devices at the I/O pads inevitably cause parasitic effects on the signal path. For the RF front-end circuits operating in the frequency band from several gigahertzes to tens of gigahertz, they have the strict limitations of the parasitic effects on the signal path in such high operating frequency. This situation leads to the challenge in ESD protection design for RF circuits, which is to achieve the highest ESD robustness with the smallest performance degradation. In other words, the parasitic effects of the ESD protection devices need to be minimized. Moreover, the evolution of CMOS process increases the difficulty of ESD protection design. As CMOS process is continuously scaled down, the power-supply voltage is decreased and the gate oxide becomes thinner, which leads to the reduced gate-oxide breakdown voltage of MOS transistor. However, ESD was not scaled down with the CMOS technology, so the MOS transistors with thinner gate oxide are more vulnerable to ESD. The aforementioned design challenges form the motivation of this dissertation. The research topics of this dissertation including: (1) ESD protection design on a 5-GHz differential low-noise amplifier with cross-coupled SCR, (2) optimization on SCR device with low capacitance for RF ESD protections, (3) ESD protection design on an ultra-wideband power amplifier with waffle-structured SCR, (4) modeling parasitic capacitance for matching network co-designed in RF ICs, and (5) high-voltage-tolerant ESD clamp circuit by using only low-voltage devices with low standby leakage in nanoscale CMOS process.
In chapter 2, the pin-to-pin ESD protection design on a 5-GHz differential LNA is proposed. The 5-GHz differential LNA is implemented in a 130-nm CMOS process. The new ESD protection scheme for differential input pads is realized with the cross-coupled SCR. This ESD protection scheme achieves 3.5-kV HBM and 300-V MM ESD levels, respectively.
SCR realized in waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance in chapter 3. The proposed waffle-structured SCR has been verified in a 0.18-µm CMOS process. The waffle layout structure of SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with waffle layout structure and its turn-on time has also been investigated in silicon chip.
In chapter 4, the waffle-structured SCR is applied to an ultra-wideband (UWB) RF power amplifier (PA). The waffle-structured SCR is designed with ESD detection and trigger circuit to provide the best ESD protection capability while contributing minimum parasitic capacitance to the RF PA in a 130-nm CMOS process. The measurement results have verified the effectiveness of the proposed ESD protection strategy and proved that this ESD protection technique indeed provides excellent ESD robustness of up to 8kV HBM ESD level and 800V MM ESD level.
As the operating frequencies of RF front-end circuits are increased, on-chip ESD protection designs for RF applications are more challenging, and they should be designed more carefully. In chapter 5, the small-signal circuit model of waffle-structured SCR has been presented and proved in silicon. The measured parasitic capacitances well agree with the simulated capacitances. The RF circuits can be well co-designed with the presented small-signal model to eliminate the negative impacts from ESD protection SCR on RF performances. Besides, the optimized design of the bond pad for RF applications was also investigated. The experimental results in a 65-nm CMOS process have proven that the bond pad capacitance and insertion loss can be successfully reduced by the optimized bond pad structure. The small-signal circuit model of the optimized bond pad has also been presented for RF circuit designs.
The efficient power-rail ESD clamp circuit must be included into the RF ICs to reduce the dimensions of ESD devices connected to the I/O pad. In chapter 6, the new 2×VDD-tolerant ESD clamp circuit by using only low-voltage devices with low standby leakage current and high ESD robustness for system-on-a-chip (SoC) applications with mixed-voltage I/O interfaces has been successfully designed and verified in a 65-nm CMOS process. The 2×VDD-tolerant ESD clamp circuit can operate without gate-oxide reliability issue, and the leakage current is only in the order of 100 nA under normal circuit operating condition. Besides, there is no latchup concern in this design. The new ESD clamp circuit by using only low-voltage devices with very low standby leakage current and high ESD robustness is the useful circuit solution for on-chip ESD protection design with mixed-voltage I/O interfaces in SoC applications.
In this dissertation, several novel designs have been proposed in the aforementioned research topics. Measured results of the fabricated test chips have demonstrated the performance improvement. The achievements of this dissertation have been published or submitted to several international journal and conference papers. Several innovative designs have been applied for patents.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411709
http://hdl.handle.net/11536/80620
显示于类别:Thesis


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