應用於系統面板之各種薄膜電晶體元件結構

Abstract

在此論文中，分別針對汲極、閘極與通道等三項工程提出不同改善結構與技術以提昇低溫多晶矽薄膜電晶體之電特性。除此之外，為使系統面板能更具多元化，我們也開發以低溫多晶矽薄膜電晶體技術為基礎之非揮發性記憶體與場發射元件。 首先，針對低溫多晶矽薄膜電晶體汲極工程的開發，有別於傳統須複雜製程或額外光罩來製做的降電場結構，我們提出僅需簡單選擇性蝕刻法與臨場真空封裝技術製作出具有真空腔洞之T型閘極低溫多晶矽薄膜電晶體，利用製做出的偏移區域(offset region)與真空腔洞可有效降低其汲極端之大電場，因而可大幅降低漏電流、提高開關電流比、降低紐結電流(kink current)、與改善可靠度問題。 其次，針對低溫多晶矽薄膜電晶體閘極工程的開發，我們提出一種簡單且低成本的方式來製作新穎環繞式閘極與多重奈米通道之複晶矽薄膜電晶體。利用簡單間隙壁技術(spacer technique)來製作高寬比趨近於一之奈米通道，而不需先進微影技術。並利用蝕刻犧牲氧化層來讓奈米通道懸空以至於能被閘極完全包覆形成環繞閘極結構。製作出的具環繞閘極與多重奈米通道之複晶矽薄膜電晶體和傳統的元件比較起來有相當良好的電特性。該元件擁有較高載子移動率、較低的臨界電壓、較高開關電流比、與極佳之短通道效應之抑制能力。這些改善主要可歸功於環繞閘極增強閘極之控制能力、奈米線中的三個尖端與較少的缺陷量。 針對通道工程的改善，我們提出兩種新穎製程方式可製作具高結晶性矽奈米線之多晶矽薄膜電晶體。第一種為控制最佳準分子雷射能量，直接對奈米線做結晶，由於利用前敘之隙壁技術會造成奈米線區域之非晶矽較薄，而汲/源區域較厚，故在雷射照射下，可控制晶種分別由汲/源區域兩區域成長過來，因而可達成只有一個晶界之奈米線，利用該法製作出的環繞式閘極薄膜電晶體擁有273 cm2/V-s之場效載子移動率。另一種，則利用奈米尺寸之氮化矽隙壁(nitride spacer)當硬光罩直接蝕刻定義奈米線在連續側向固化結晶法(sequential-lateral-solidification)之大晶粒多晶矽薄膜上，由於奈米線尺寸遠小於大矽晶粒的尺寸，故可製作出幾乎是單晶的矽奈米線，利用該法製作出的環繞式閘極薄膜電晶體擁有596 cm2/V-s之場效載子移動率與極陡之次臨界擺幅(101 mV/decade) ，因此非常適用於未來系統面板(system-on-panel)的應用。 針對非揮發性記憶體開發，我們提出利用隙壁直接造成的三個尖端之電場增強式奈米線，使有效的提高SONOS (silicon-oxide-nitride-oxide-silicon)記憶體之寫入/抹除效率。除此之外，我們也第一次提出將穿隧氧化層置換成真空之SONVAS (silicon-oxide-nitride-vacuum-silicon)結構，由於穿隧層為為最低介電係數之真空，所以亦可進一步將穿隧層之電場提高，因而可進一步提高記憶體之寫入/抹除效率；且穿隧層為真空，可以降低傳統因多次寫入/抹除對穿隧氧化層造成的傷害，因而也可大幅提升其耐久(endurance)可靠度。 針對場發射顯示開發，我們也利用以低溫多晶矽為基礎之隙壁技術(spacer technique)製作兩種場發射元件，使其有機會能直接整合於系統面板上而取代傳統液晶顯示器。第一種為直接以隙壁矽奈米線之尖端當成場發射源，其導通電場為2.06 V/µm。此外，我們也利用前敘之環繞式電極直接當成陽極，懸空之三個尖端隙壁奈米線當成陰極，直接由E-Gun沉積的二氧化矽封成真空，利用該法製作出場發元件，導通電壓僅0.14 V，為目前最低的導通電壓。 最後，該論文結論與針對未來系統面板研究可著重的工作方向亦討論之。

In this thesis, various structures and techniques are studied for the fabrication of high-performance low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) through drain, gate, and channel engineering. In addition, for further versatile system-on-panel (SOP) applications, the novel nonvolatile memories and field emitters based on LTPS technology are developed as well. At first, for drain engineering, the T-shaped-gate (T-Gate) LTPS TFTs with symmetric vacuum gaps have been proposed and fabricated simply only with a selective-etching technique and an in-situ vacuum encapsulation. Due to the great reduction of electric field near the drain junction by the resulting offset region and vacuum gap, the fabricated T-Gate LTPS TFTs exhibit ultra low leakage current, high on/off current ratio, reduced kink current, and high reliability. Secondly, for gate engineering, the novel gate-all-around (GAA) poly-Si TFTs with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple process to demonstrate high performance electrical characteristics and high immunity to short channel effects (SCEs). The nanowire channel with high body thickness-to-width ratio, approximately equals to one, is realized only with a sidewall-spacer formation. Moreover, the unique suspending MNCs are also achieved to build the GAA structure. The resultant GAA-MNC TFTs show outstanding three-dimensional gate controllability and excellent electrical characteristics, which reveal a high on/off current ratio, a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering, as well as an excellent SCE suppression. For channel engineering, two types of novel processes are subsequently demonstrated for fabricating high-crystallinity Si-nanowire LTPS TFTs. The one is to utilize the previously proposed sidewall-spacer nanowire structure to control the lateral grain growth from the thicker S/D pads to the center of thinner nanowire channel. Due to the necking effect in such nanowire structure, only-one grain boundary exists in the middle nanowire channel. LTPS TFTs with field-effect mobility of 273 cm2/V-s have been fabricated by using this method. The other is to utilize spacer lithography to directly transfer the nanowire pattern onto the large-grain sequential-lateral-solidification (SLS) poly-Si thin film. In term of probability, the nanowire pattern (8 nm) is much smaller than the SLS grain width (0.8 μm), which makes the nanowire locate within a single grain, thus the resulting nanowire can be performed like a single-crystal simply. Due to the high-crystallinity formed in the nanowire channel, the nanowire TFT exhibits an excellent mobility of 596 cm2/V-s and steeper subthreshold slope of 101 mV/decade. As a result, it is very suitable for future system-on-panel (SOP) applications. For nonvolatile memory development, a field-enhanced nanowire (FEN) LTPS-TFT silicon-oxide-nitride-oxide-silicon (SONOS) memory with a gate-all-around (GAA) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently has three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carriers tunneling via such a structure lead to faster P/E speed and wider memory window for the FEN SONOS as compared to the conventional planar (CP) counterpart. The FEN LTPS TFT SONOS device exhibits a Vth shift of 2.71 V and 2.11 V at VGS = +15/-15 V in 1 ms for FN programming and erasing (P/E) operations, respectively. Other than FEN structure, a vacuum counterpart is further as a substitute for tunneling oxide to perform the novel silicon-oxide-nitride-vacuum-silicon (SONVAS) structure, for the first time. Due to the further electric field enhancement from the vacuum introduction in tunneling layer, the FEN SONVAS exhibits larger Vth shifts of 3.17V and 2.68V at VGS = +15/-15V in 1 ms for FN P/E operations, correspondingly. Besides, due to the empty property of vacuum, there are less dangling bonds and tunneling-oxide traps produced during P/E cycles, so that FEN SONVAS exhibits much improved endurance reliability as well. For field emitter development, spacer technique are applied on two types of LTPS-based field emitters for the possibilities of the replacement of LCD display elements in terms of system integration and image performance. For spacer nanowire field emitters, the F-N characteristics with turn-on field of 2.06 V/um have been performed. For the triple-corner nanowire emitter in-situ vacuum-encapsulated by the surrounding silicon dioxide, the F-N characteristics have been performed with a turn-on voltage of 0.14 V, which is the lowest one in the record to date. Finally, conclusions as well as prospects for further research are also summarized.