高速音圈馬達位置控制之FPGA晶片研製

Abstract

本論文以場效型可規劃邏輯陣列(FPGA)晶片為基礎，整合數位邏輯晶片與Nios II處理器於單一顆FPGA晶片中，以實現高速音圈馬達之位置控制，在數位邏輯晶片中，將以硬體描述語言實現類比數位轉換器(A/D Converter)以及數位類比轉換器(D/A Converter)功能模組；而在Nios II處理器中，將以C語言實現音圈馬達之速度PI控制器、位置P控制器以及位置估測演算法則。

在實驗系統的建構方面，採用Altera公司Cyclone II系列的Nios II Development Board為音圈馬達的控制核心，並配合一套包含驅動處理、訊號調整、訊號取樣、訊號輸出功能的外部電路，來完成音圈馬達位置控制系統的架構，並經由實驗數據的量測分析與控制參數的調整，來獲取系統較佳的控制效能表現。

本次研究的結果，能將自動對焦系統的響應時間減少在60至80毫秒，穩態誤差在10\%以內，而這10\%穩態誤差來自於磁性尺的先天缺陷，例如像磁阻式感測器量測各個極距的振幅大小不同。而音圈馬達最大電流僅消耗30毫安培，這對於省電功能也將有莫大的助益。

In this thesis, a FPGA(Field Programmable Gate Array)-based Chip design is taken to implement a position control chip conceptual core for high speed voice coil motor(VCM) drive, and the control chip integrate digital logic IC and Nios II processer in single FPGA chip. The function of the digital logic IC includes analog/digital Converter and digital/analog Converter. And the function of Nios II processor includes speed-loop proportional-integration(PI) controller, position-loop proportional controller, and position estimation algorithm.

As for the experimental setup and related system collocation, it is construct from the Altera Cyclone II Nios II development board of the core concept for controlling a VCM, and peripheral circuit boards for motor drive, signal regulate, signal sample,and signal output function. Besides, it demonstrates the effectiveness of the proposed FPGA-based control system for the performance improvement for VCM drive can be achieved by adjustment of the conreol parameter and measurement and analysis of experimental data.

The results of this study, the responsed time needs about 60∼80 ms with the 10% steady-state error; the 10% steady-state error is caused form the defects of the magnetic scale such as the variations of the amplitudes of the MR sensor signals. The maximum current consumption of the VCM in this study is about 30 milliampere (mA), this advantage can save more battery energy of the DVC.