每秒五十億次取樣六位元類比數位與數位類比轉換器之設計

Abstract

本論文提出一組每秒五十億次取樣六位元之快閃式類比數位轉換器與電流式數位類比轉換器對設計，並使用台積電0.13μm CMOS Mixed-Signal RF製程實現。此組資料轉換器對可應用於高速串列傳輸收發機。在類比電路的前置放大器中，我們利用主動式負回授技巧使其能達到較高之頻寬，同時運用平均與內插的方式來降低放大器的偏移誤差量與減少所需之放大器數目。而數位電路部分則是採用電流式邏輯電路設計，電流式邏輯可大幅抑制電源抖動量，且由於其是操作在較低擺幅，故所需之功率消耗較少、運作速度較快。量測結果顯示，在5GS/s的取樣頻率下，對串接在一起之類比數位轉換器與數位類比轉換器輸入一0.5GHz、-1dBFS的弦波訊號時，可得36.98 dB的訊號對雜訊比。若更進一步操作在6GS/s，輸入相同之測試訊號，則此資料轉換器對的訊號雜訊比仍有36.977 dB。在 1.2V電源供應下，此類比數位轉換器與數位類比轉換器分別消耗655mW和115mW之功率。

This thesis presents a 5GS/s 6-bit flash analog-to-digital converter (ADC) and current-steering digital-to-analog converter (DAC) pair in TSMC 0.13μm CMOS Mixed-Signal RF technology for serial-link transceiver designs. Active- feedback technique makes the analog pre-amplifiers achieve higher bandwidths. Averaging and interpolating skills were applied to reduce the offsets and the number of the amplifiers. For digital circuitry, current mode logic (CML) gates were used to alleviate the severe power-ground bouncing. The CML gates operate at lower input/output swing resulting in lower power consumption and a higher speed. The measurement results show that the cascaded ADC and DAC pair achieves a 36.98 dB signal- to-noise ratio with the 0.5GHz, -1dBFS sinusoidal input at 5GS/s. Furthermore, this data converter pair presents a signal-to-noise ratio of 36.977 dB with the same stimulus but running at 6GS/s. The ADC and DAC dissipate 655mW and 115mW respectively from a 1.2V supply.