適用於展頻時脈與資料回復電路之漸增數位化頻率補償

Abstract

本論文設計一時脈與資料回復電路應用在展頻技術下。在一全數位化的時脈與資料回復電路中，加上另一迴路，以補償在展頻技術下產生的較大的頻率變動。在固定的頻率補償週期內，偵測頻率的變化，再頻率補償迴路中，產生等效之補償量以調整回復時脈。利用此想法，漸漸地追鎖在展頻下的頻率變化。此外，並藉由此論文分析系統中信心計數器大小的選擇方式，並設計一可調整大小之信心計數器以調整系統之等效頻寬。

於此論文中，我們實現了一個傳輸速度為每秒三十億位元的時脈與資料回復電路。使用台積電 0.18um 1P6M CMOS製程。在1.8伏特的電源供應下，所消秏60.8mW的功率，且此時脈與資料回復電路之面積為390um×400um。由模擬結果顯示，此電路可以成功地補償在Serial ATA 規格下的33kHz三角波調變率及5000ppm展頻量。

In this thesis, we design a Clock and Data Recovery(CDR) circuit for spread spectrum data communication. We add a frequency compensation loop in an all digital CDR. This frequency compensation technique compensate large frequency variation in spread spectrum data. We detect the frequency variation in a fixed period and generate the equivalent pulses to compensate frequency. Using this concept, we track the frequency variation in spread spectrum gradually. Besides, we analyze mathematically to the determinate the confidence counter size. And we design a variable size confidence counter to adjust the equivalent bandwidth.

A 3Gb/s CDR for Serial ATA is implemented in this thesis by TSMC 0.18um 1P6M CMOS technology. The proposed CDR consumes 60.8mW on a 1.8V power supply and the area is 390um×400um. It is verified that this CDR compensates the frequency variation from Serial ATA spread spectrum specification successfully.