邊界模式功率因數修正控制IC控制架構之研究與TDA4863晶片設計之電腦模擬分析

Abstract

本論文針對低功率應用且目前所使用最普遍的邊界模式PFC控制IC，分析其控制架構的特色優點，並且參考英飛凌公司的邊界模式PFC IC TDA4863的規格，從系統規格需求的觀點，以IC設計與實現為考量，探討IC內部子電路規格對系統的影響。本論文重點在研究誤差放大器之開路頻寬與增益、乘法器增益和線性度、以及比較器之遲滯比較帶寬度，在全域輸入電壓(90~265 VAC)皆可使用的條件之下，所受到一些IC電路實現上的限制以及對系統效能所造成的影響。在功率開關之閘極驅動緩衝電路的部份，本論文同時亦考慮功率損耗與傳輸時間延遲，做最佳化的分析與設計。 本文利用PSIM的系統模擬分析，探討IC內部各個子電路的規格對系統功率因數、輸入電流總諧波失真等的影響，從IC電路實現的角度為考量，藉以決定子電路的規格。根據分析整理，利用TSMC 0.35 μm製程設計一個應用於輸出功率80 W、輸出400 V的邊界模式PFC控制IC，以功率因數超過97%且總諧波失真低於10%為一設計的依據，實現其誤差放大器、乘法器、比較器、RS正反器以及閘極驅動緩衝電路，並使用Hspice模擬驗證設計。為了觀察電路實現所產生的特性差異，本論文分別以IC電路模擬為導向的Hspice與以功能方塊模擬為導向的PSIM進行模擬，比較在理想情況與實際電路實現所產生的差異。本論文分析此PFC IC子電路實現限制與系統規格間的關係，在可接受的系統規格條件下，能夠達到最佳化之設計目標。

This thesis focuses on control architecture of a boundary mode PFC IC based on TDA4863 which is generally used for the applications of low power. The effects of the sub circuit specifications on the PFC IC are analyzed to design and implement from system viewpoint. The thesis emphasizes to study the finite DC gain and bandwidth of the voltage error amplifier, gain and linearity of the multiplier and hysteresis band of the comparator, and analyzes the limitations of integrated circuit implementations and the affection to the system under the universal full rage (90 ~265 VAC). And then optimum design of the gate driver is presented that considers the power consumption and the propagation delay. This thesis utilizes PSIM for system simulation to analyze the effects of the sub circuit on the PF and the input line current THD of the system, and considers the IC implementations to determine the specifications of the sub circuits. According to the analysis, a boundary mode PFC IC which is used for the application of output power 80 W and voltage 400 V is designed by TSMC 0.35 μm process. The implementations of the error amplifier, analog multiplier, comparator, RS flip-flop and the gate driver are utilized Hspice to verify the design that the power factor exceeds 97% and total harmonic distortion is lower than 10%. To observe the different characteristic of the circuit implementation, the nonideal effects of sub circuits from the Hspice results are compared with the ideal sub circuits from PSIM. According to the study and analysis of this thesis, the boundary mode PFC IC is easily implemented and optimum designed under the acceptable performance of the system.