一個以弦波最小誤差為基礎適用於混合訊號電路之自我測試系統設計

Abstract

本論文的研究分為兩部分。首先，我們提出一個使用三階 調變器於數位震盪器的設計，以改善以最佳符合控制弦波(Control sine wave fitting)方法為基礎之自我測試設計 調變器的測試頻寬。該設計已經利用0.35um製程完成下線。經測量結果驗證所提出之設計確實可以將原有的6KHz測試頻寬提高至16KHz。此外，我們提出一個以弦波最小誤差為基礎適用於混合訊號電路之自我測試設計方法，其最大的優勢為能自動地補償相位誤差，使得此自我測試設計可以應用在一般的混合訊號電路設計上。再搭配使用所提出的寬頻域極點補償型數位弦波產生器，便可以提供更精準的測試結果與更寬的測試頻寬。我們採用一個具可數位測試設計的□□□類比數位轉換器作為待測電路，並利用FPGA實現了一個完整的混合訊號自我測試電路。量測結果顯示，所提出之自我測試電路設計方法可以測得76 dB的SNDR峰值，且其測試頻寬可高達24KHz。所需的額外硬體成本僅23.1K個邏輯閘。

This thesis is divided into two parts. First, we propose the 3rd-order modulator based digital oscillator to improve testing bandwidth of the BIST modulator based on the control sine wave fitting (CSWF) method. A test chip has been tapouted using a 0.35□m CMOS process. The measurement results show that with the proposed digital oscillator, the testing bandwidth can be enhanced from 6 KHz to 16 KHz. On the other hand, we also proposed the sinusoidal minimum error method based (SME) BIST scheme for mixed signal circuits. The major advantage of the SME BIST scheme is that it automatically compensates the circuit under test for its phase delay. With the help of the proposed novel wide-band compensation type digital oscillator, the SME BIST modulator can achieves a wider testing bandwidth. We use the same circuit under test and FPGA to verify our design. The measurement results show that the testing bandwidth can be higher than 24KHz and a 76 dB peak SNDR can be measured. The hardware overhead is as low as 23.1K gates.