考慮晶片上具有空間相關製程變異的統計型晶片熱分佈模擬器

Abstract

傳統上晶片上熱分佈分析主要是考慮不具隨機性的功率消耗的熱傳方程式，然而，隨著製程的演進，導致在參數如電晶體通道長度和氧化層厚度的變異波動對於電路的效能、功率消耗、可靠度上有重大的影響。在晶片設計階段時忽略製程上的變異將會造成嚴重的良率問題。在這篇論文，我們提出一個方法分析晶片上統計型溫度分析考慮晶片上具有空間相關的製程變異。這篇論文是第一篇考慮晶片上具有空間相關製程變異的統計型晶片熱分佈模擬器，利用卡洛轉換Karhunent-Loeve transformation)處理具有空間相關隨機過程並且利用正交多項式(Polynomial Chaos)和隨機加勒金法(Stochastic Galerkin method)解統計型熱傳方程式。與蒙地卡羅模擬法(Monte Carlo simulation)比較來說明我們所提出方法的正確性和效率性。模擬的結果可以保證提供可靠的溫度分佈良率，並且指引設計者去避免晶片熱毀壞的問題在次微米半導體時代。最後我們更指出提供精確的晶片上溫度分佈不能忽略空間相關製程變異。

Traditionally, the thermal analysis methods of chip have been conducted by solving the heat transfer equation with deterministic heat sources. However, the technology scaling leads to that the fluctuations in physical parameters such as channel length and oxide thickness have a substantial impact on circuit performance, power consumption, and reliability. Ignoring the manufactured process variations at the design stage can cause aggravated yield losses. In this paper, we present a method to analyze the statistical temperature distribution of full chip under considering process variations with a known within-die spatial correlation function. To the author’s best knowledge, this is the first stochastic thermal simulator of full chip with considering within-die process variations. This work makes use of the Karhunen-Loeve transformation to deal with the physical parameters with spatial correlation and takes advantage of polynomial chaos and stochastic Galerkin method to tackle the stochastic heat transfer equation. We demonstrate the accuracy and efficiency of the proposed methodology in comparison to Monte Carlo simulation. The simulation results guarantee the robust thermal yield and can guide designers to avoid the thermal failure in nano-meter technology. Furthermore, we point out that the within-die spatial correlation can not be neglected for the accurate temperature estimation.