連續時間轉導電容式三角積分調變器之實現

Abstract

由於近年來無線通訊蓬勃發展，因此適用於無線通訊中的類比數位轉換器也受到更大的矚目。一般無線通訊常為窄頻通訊，為了簡化架構通常希望類比到數位轉換器在頻帶內可有更高的抗雜訊能力。另一方面也希望能夠在低電壓、低功率下操作，因此，一個高解析度、低功率耗電且面積小的類比數位轉換器是很重要的。而三角積分類比數位轉換器就非常符合這個需求，因為它在有限頻寬的限制下可以達到非常高的解析度。除此之外，類比所佔的成份也相對比較少且對製程漂移的影響也比較小。因此，近幾年來三角積分類比數位轉換器都扮演著非常重要的角色。

三角積分類比數位轉換器在不同的應用範圍下通常會有兩種種類，一種是離散時間三角積分類比數位轉換器，因為它通常都是用交換電容的電路下實現，所以又稱為交換電容三角積分類比數位轉換器。早期論文以離散時間三角積分類比到數位為主，但是2002年以後，連續時間三角積分類比到數位則大量的被發表。原因為連續時間三角積分通常對於運算放大器的要求比較寬鬆，它不需要在一個clock的時間下做處理，所以耗費功率比較低，而且具有Anti-aliasing的性質。

因此，為了將連續時間三角積分類比數位轉換器的優點應用在通信的範圍內，此研究主題就是做出一個適用於GSM系統200k赫茲頻帶、取樣頻率20MS/s的低功率三階零點最佳化的連續時間轉導電容三角積分類比數位轉換器，以符合可攜式電子產品需要低消耗功率的趨勢。

晶片是以台積電0.18微米標準互補式金氧半導體製程所製造。在200k赫茲頻帶內的量測結果為：最大訊號雜訊失真比為45dB，訊號雜訊比為47.8dB，動態範圍是49dB，解析度為7.2位元，與預測結果相差約4位元。

Because of the rapid growth of wireless communication, there has been more focus on analog-to-discrete converter (ADC) for wireless communication. Since the frequency is usually narrow-band in general wireless communication, in order to reduce the complexity of the architecture, we usually require the ADC has the ability of in-band anti-noise. Besides, it is important the ADC operates in low voltage, low-power, and small area. The delta-sigma (ΔΣ) ADC is very suitable for the application because they can achieve high accuracy for narrow band signals with few analog components and insensitivity to process and component variation.

Typically, there are two kinds of ΔΣ ADCs. The first one is the discrete-time (DT) ΔΣ ADC and the other is the continuous-time (CT) ΔΣ ADC. The DT ΔΣ ADC also called the switched-capacitor (SC) ΔΣ ADC because of using switched capacitors. The CT ΔΣ ADC obtains lots of attentions lately. Because the requirement of integrator is relaxed, it does not need to process signals within a clock time. This results in further power reduction.

In order to combine the advantages of the CT ΔΣ ADC system into low-power communication system, this research focuses on low power 20MS/s sample frequency 3-rd order zero optimization CT GM-C ΔΣ ADC for GSM communication system.

The chip has been fabricated by TSMC 0.18-um CMOS process. The measured peak SNDR is 45dB, SNR is 47.8dB and the DR is 49dB. The resolution is 7.2 bits that is 4 bits lower than prediction in 200k HZ signal band.