完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, T. | en_US |
dc.contributor.author | Kao, H. L. | en_US |
dc.contributor.author | McAlister, S. P. | en_US |
dc.contributor.author | Horng, K. Y. | en_US |
dc.contributor.author | Chin, Albert | en_US |
dc.date.accessioned | 2014-12-08T15:10:35Z | - |
dc.date.available | 2014-12-08T15:10:35Z | - |
dc.date.issued | 2008-12-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2008.2007509 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/8088 | - |
dc.description.abstract | We have fabricated 0.18-mu m asymmetric MOSFETs using a foundry-standard 1P6M process, without making any process modifications. In comparison with a conventional 0.18-mu m MOSFET, the asymmetric MOSFET design leads to a 64% improvement in the saturated output power and 8 dB better adjacent channel power ratio. The improvement in the RF power E performance of these MOS transistors suggests that they should be suitable for medium power amplifiers. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Asymmetric | en_US |
dc.subject | lightly doped-drain (LDD) | en_US |
dc.subject | MOS | en_US |
dc.subject | RF Power | en_US |
dc.title | Improved RF Power Performance in a 0.18-mu m MOSFET Which Uses an Asymmetric Drain Design | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2008.2007509 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 29 | en_US |
dc.citation.issue | 12 | en_US |
dc.citation.spage | 1402 | en_US |
dc.citation.epage | 1404 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000262062000035 | - |
dc.citation.woscount | 4 | - |
顯示於類別: | 期刊論文 |