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dc.contributor.authorWu, CCen_US
dc.contributor.authorChen, Cen_US
dc.date.accessioned2014-12-08T15:01:11Z-
dc.date.available2014-12-08T15:01:11Z-
dc.date.issued1998-01-01en_US
dc.identifier.issn0253-3839en_US
dc.identifier.urihttp://hdl.handle.net/11536/80-
dc.description.abstractAccording to published research results, no directory-based cache coherence protocol provides best performance for all application programs in conventional multiprocessor systems that use sequential consistency models. However, recently it has been claimed that competitive-update protocols are superior to other protocols under a relaxed consistency model. Moreover, incorporating write caches improves the system performance of clean and competitive-update protocols. In this paper, we examine the different effects that occur when processing elements are replaced by parallel-multithreaded processors. According to our simulation results, the clean protocol provided the best performance for five out of six SPLASH programs. After augmentation with write caches, the clean protocol outperformed others for all applications. Though competitive-update protocols have been improved, their performance is not better than that of write-invalidate protocols for most programs.en_US
dc.language.isoen_USen_US
dc.subjectwrite cacheen_US
dc.subjectmultithreaded processoren_US
dc.subjectshared-memory multiprocessoren_US
dc.subjectcache coherence protocolen_US
dc.titleA performance study of cache coherence protocols and write coaches for parallel-multithreaded shared-memory multiprocessorsen_US
dc.typeArticleen_US
dc.identifier.journalJOURNAL OF THE CHINESE INSTITUTE OF ENGINEERSen_US
dc.citation.volume21en_US
dc.citation.issue1en_US
dc.citation.spage33en_US
dc.citation.epage46en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
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