全閘極複晶矽薄膜電晶體暨電路數值模擬之研究

Abstract

本論文主要探討全閘極複晶矽薄膜電晶體暨電路數值之模擬。首先吾人運用數值方法離散載子流連續程式及泊松方程式，這些方法包含有Gummel's 疊代法，有限體積近似法，以及牛頓法來解一組半導體偏微分方程式。在薄膜電晶體模式中應該考慮適當的晶粒邊界效應，一般而言晶粒邊界的位障模式和電位能是複雜的非線性函數關係，當代入半導體偏微分方程式時，會造成離散複雜化，使得網格加切數量增加以及計算時間增長。經由與實驗數據之校估，萃取出晶粒邊界之缺陷濃度以及缺陷能障。 藉由萃取出的晶粒邊界參數，分析縮小通道尺寸的問題。當通道尺寸在三百奈米時，也就是約等於一個晶粒大小時，元件會面臨到有、無晶粒邊界的問題，吾人探討單晶粒邊界發生在通道不同位置所造成元件特性漂移的情形。相較於晶粒邊界發生在通道中間或者沒有晶粒邊界的情形，汲極端若有晶粒邊界會產生顯著的臨界電壓變化。晶粒邊界變小，臨界電壓變化會逐漸降低。研究結果的比較顯示，深次微米全閘結構複晶矽薄膜電晶體，比傳統單閘結構複晶矽薄膜電晶體特性來的穩定性好兩倍以上。全閘結構複晶矽薄膜電晶體更有以 下優點: (1) 電子遷移率上升，(2) 因有較好的閘極控制通道能力，故有較低的汲極電壓致使能障降低效應 (DIBL)、較低的次臨界震盪 (S.S)，並且藉由輕汲極摻雜(LDD)，提高開/關電流比，加快元件切換速度。(3) 較小的臨界電壓變化，提升主動式矩陣電路驅動電流的穩定性。 研究上更探討量子修正模式之九十奈米全閘結構複晶矽薄膜電晶體，晶粒邊界大小及發生位置對臨界電壓變化的影響，也一倂分析。若晶粒邊界的大小可以控制2奈米以下，臨界電壓的變化和晶粒邊界發生的位置就無關。 因為全閘極複晶矽薄膜電晶體沒有相對應的模式，無法萃取出元件的等效參數，若要進行電路模擬必有極大困難。吾人研究一套不需要萃取出元件參數的方法，而直接進行三維度元件暨電路模擬 (Mixed-Mode)。結果顯示，以全閘極結構複晶矽薄膜電晶體組成之電路具有快速切換開關的能力，和工業標準之單閘極複晶矽薄膜電晶體電路比較，有9 倍以上的改良。 總之，本研究已經藉由元件結構的改良，研究了複晶矽薄膜電晶體基本電特性以及驅動電路的性能；期盼低溫複晶矽製程技術的成長，未來希望能將顯示電路應用在玻璃基板上，使得面板電路積體化可以實現。

This thesis numerically simulates gate-all-around (GAA) poly-Si thin film transistors and circuits. Firstly, the Poisson's and drift-diffusion equations are decoupled according to Gummel's procedure. Based on adaptive one-irregular mesh, each decoupled partial differential equation (PDE) is discretized and then solved iteratively using Newton's method. Since the barrier height and potential of the grain boundary (GB) are complex non-linear functions, the computational time is very large. After calibration with reference to measurements, the barrier height of GB equals 0.15 eV and the concentration of GB is approximately 3E13/cm2. Based on the extracted parameters of GB, the performance of poly-Si TFTs on the sub-micron scale is analyzed. When the channel length is 300 nm, it is approximately the size of one grain. The effects of GB at various positions are investigated. The position near the drain side exhibits a large variation in the threshold voltage (Vth). This effect can be suppressed by GAA poly-Si TFTs: the variation of Vth can be reduced to 5 % of that of single gate (SG) poly-Si TFTs. GAA poly-Si TFTs also have the following advantages. (1) The mobility of the electron increases. (2) The excellent channel controllability due to the natural infinite gate is such that the drain-induced barrier is lowered (DIBL) and the subthreshold swing (S.S) reduced. A lightly doped drain (LDD) profile is considered to reduce the leakage currents; the On/Off ratio increases. (3) The smaller variation of Vth makes the current in the active-matrix driving circuit more stable. Additionally, 90 nm GAA poly-Si TFTs are simulated using quantum correction models. If the size of GB is maintained within 2 nm, the variation of Vth is independent of the position of GB. Since the GAA poly-Si TFTs have no compact device models, the simulation of the active-matrix driving circuit seems to be impossible. A three-dimensional simulation of devices coupling circuits is developed and compact models are not required. The procedure is called the mixed-mode method. For 2T1C and 4T2C active-matrix driving circuits, the results reveal that the switching speed of GAA poly-Si TFTs can be improved by a factor of nine above that obtained using SG poly-Si TFT circuits. We further simulate Goh’s active-matrix driving circuit and the variation of OLED is reduced to 0.01 V. Changing the structure of poly-Si TFTs can markedly improve the performance of devices and circuits. We hope for many display applications and the successful use of integrated circuits.