應用新穎低溫微波退火製程製作奈米級薄膜電晶體之分析研究

Abstract

在本研究中，我們在攝氏300度低溫環境中，成功製作出線寬僅80奈米且具有高性能之薄膜電晶體，其中我們特別應用新穎低溫微波退火製程技術處理奈米級薄膜電晶體的源極/汲極活化步驟。微波退火活化製程與傳統的熱退火活化製程在本質上有著很大的不同點，其中我們也藉由量測元件的電性及分析其物理特性來探討二者間的差異性。微波退火活化技術的低溫特性，適當的抑制了源極/汲極活化步驟中，離子佈子摻雜物的過度擴散。因此新穎低溫微波退火製程技術對於閘極感應汲極漏電(GIDL)及短通道效應(SCE)的抑制提供了可行的解決之道。我們也運用了四端點片電阻測試結構量測出閘極及源極/汲極的片電阻值，藉此驗證了微波退火活化技術對於離子佈植摻雜物可有效的完全活化。另一方面，由於微波退火活化技術的低溫特性可避免異質接面的缺陷與晶格錯位等問題的發生，未來將有助於將其應用於三維積體電路結構、矽鍺通道電晶體及各種化合物半導體元件之製程中。

In this thesis, we demonstrated a nano thin film transistors with channel length of 80 nm and high performance fabricated at very low temperature at 300℃. We applied a novel low temperature microwave annealing technique to activate the source/drain junction of nano thin film transistors successfully. Microwave annealing process is a different annealing process from conventional rapid thermal process (RTP) intrinsically. We discover the difference between microwave annealing and the conventional thermal annealing process in the electronic and physical properties of device performance. The low-temperature process of microwave annealing suppresses the excessive diffusion and expansion of dopants during the source/drain activation process. As a result, novel low-temperature microwave annealing process provides a applicable solution for the issue of gate induced drain leakage (GIDL) and short channel effect (SCE). Determining the sheet resistance of gate and source/drain junction by using four-terminal sheet resistance test structure verifies the activation process is accomplished by means of microwave annealing process. On the other hand, due to the property of low-temperature process, microwave annealing would not result in any defect or misfit dislocation at the interface of heterogeneous structure which can be applied to 3D-ICs, transistors with SiGe channel, and other semiconductor compounds.