標題: 應用集群分析設計晶圓量測點之抽樣與模擬方法
A Sampling and Simulation Method for Measurement Points on Wafers Using Clustering Analysis
作者: 呂祐銘
Yu-Ming Lu
唐麗英
洪瑞雲
Lee-Ing Tong
Ruey-Yun Horng
工業工程與管理學系
關鍵字: 集群分析;晶圓量測點;模擬;抽樣方法;Clustering Analysis;Wafer Measurement Points;Simulation;Sampling Method
公開日期: 2006
摘要: 近年來半導體產業為降低生產成本,除將晶圓尺寸增大以便切割出更多的晶方外,並致力於提昇晶圓之品質與良率。在提昇晶圓品質方面,由於晶圓尺寸不斷地增加,在晶圓面積小時尚能以晶圓上之少數幾個特定位置之量測點來模擬晶圓表面其它位置之量測點資訊,當成晶圓品質之真實資訊,但在晶圓面積不斷增大下,利用小晶圓面積上原先少數量測點位置所得之資訊已不能準確地模擬出大面積晶圓所有量測點之實際品質資訊。此外,由於晶圓的檢驗工作相當費時,雖然晶圓量測點越多,越能得到真實的晶圓品質資訊,但量測成本也會隨之大幅增多。因此本論文之主要目的是針對大面積之晶圓發展一套晶圓量測點之抽樣與模擬方法在晶圓表面上決定一些具代表性的量測點位置,然後再根據這些量測點來模擬出其它量測點,以有效降低量測成本及獲取準確之晶圓資訊。本論文首先利用集群分析(Clustering Analysis)找出晶圓上晶方(die)之品質特性量測值的區塊分佈情況,進而選擇一些特定晶方的量測位置,並依據這些晶方之資訊模擬出其它未檢驗之晶方的量測點之品質資訊。本論文所提出之模擬晶圓量測點的方法,可提供工程人員明確之量測點的檢驗數目與位置,不僅能有效反映出晶圓之真實品質資訊,且能降低晶圓檢驗成本與時間。本論文最後以新竹科學園區某積體電路廠所提供之真實八吋晶圓資料,驗證了本研究方法的有效性。
In recent years, the semiconductor industry reduces the production costs by increasing the wafer size and enhancing the yield. When the wafer size is small, the quality information of a wafer can be obtained by measuring few fixed-points on a wafer. As the wafer size increases, few fixed-points on wafer are no longer sufficient to provide adequate information to correctly estimate the wafer quality characteristic. However, because the wafer inspection procedure is quite time-consuming and costly, more measurement points will increase the inspection cost. Therefore, the objective of this study is to design a sampling and simulation method for measurements on wafers. First, a few representative measurement points are sampled. These measurement are utilized to simulate other points on wafers to reduce the sampling cost and obtain sufficient wafer information. The proposed method utilizes clustering analysis to analyze the distribution of wafer measurement points. The results are utilized to decide the position of the representative die measurements. Simulated measurement points are obtained using the representative measurement points for other positions of the die measurements which are not sampled. The proposed method can reduce the inspection cost and cycle time. Actual 8-inch wafer data from an integrated circuit company in Taiwan are used to verify the effectiveness of the proposed procedure.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009433503
http://hdl.handle.net/11536/81610
顯示於類別:畢業論文