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dc.contributor.authorCheng, JYen_US
dc.contributor.authorLei, TFen_US
dc.contributor.authorChao, TSen_US
dc.contributor.authorYen, DLWen_US
dc.contributor.authorLin, CJen_US
dc.date.accessioned2014-12-08T15:02:07Z-
dc.date.available2014-12-08T15:02:07Z-
dc.date.issued1997-01-01en_US
dc.identifier.issn0013-4651en_US
dc.identifier.urihttp://hdl.handle.net/11536/817-
dc.description.abstractTwo planarization approaches of the oxide-filled trench isolation have been evaluated. Results show that the oxide-filled shallow-trench isolation technology based on a chemical-mechanical polishing (CMP) process is difficult to control and has a poor uniformity. It also results in a dishing effect in wide field regions. On the other hand, a new planarization process can achieve an excellent uniformity and fully planar surface by using a combination of a masking polysilicon layer based on a CMP process, selective wet etching for oxide refill on active regions, short-time CMP process for oxide refill, and reactive ion etching etchback. Results also show that the high breakdown yield of the gate oxide and the low leakage current of the n(+)/p junction diodes with the novel planarization process demonstrates extremely low defect density from this process. This new process is a very promising candidate for oxide-filled shallow-trench isolation.en_US
dc.language.isoen_USen_US
dc.titleA novel planarization of oxide-filled shallow-trench isolationen_US
dc.typeArticleen_US
dc.identifier.journalJOURNAL OF THE ELECTROCHEMICAL SOCIETYen_US
dc.citation.volume144en_US
dc.citation.issue1en_US
dc.citation.spage315en_US
dc.citation.epage320en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department奈米中心zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentNano Facility Centeren_US
dc.identifier.wosnumberWOS:A1997WG07000051-
dc.citation.woscount15-
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