考慮干擾效應非點格式繞線系統的研發與整合

Abstract

隨著超大型積體電路製程技術邁入奈米時代，使得電子裝置的大小及線路的寬度都隨之縮小，而且在相同層中，線路間的距離也變得越來越近。一條不良繞線品質的長訊號(訊號線長度過長以及與相鄰導線平行長度過長而引發的藕合效應)將會產生過多的延遲。因此在高速超大型積體電路的設計中，想辦法避免或滿足電磁干擾效應的重要性也隨之提升。然而，在傳統的兩階段繞線：全域繞線(Global routing)和精細繞線(Detailed routing) 流程中，要解決這樣的問題會使得整個流程變得複雜且沒有效率。因為在全域繞線中，沒有電路線軌的資訊，所以很難去考量電磁干擾現象;而在精細繞線這原本就十分耗時的階段去考量此問題，只會增加它大量的計算，使它的負擔變的更重。因為這些原因，有人便提出了在全域繞線及精細繞線中併入一個中間的步驟，稱之為電路線軌指派(Track assignment)。 這份論文將著重於非點格式繞線系統，並且將線軌指派演算法整合入傳統的兩階段非點格式繞線系統。在最後的實驗數據中，將會發現在非點格式繞線系統中，比起傳統的二階段繞線系統，三階段繞線系統將得到較快的繞線速度，另外也針對非點格式線軌指派階段發展減少藕合效應的指派演算法以產生較佳的結果佈局。

As the VLSI manufacturing technology advances to the Very Deep Submicron(VDSM) era, the device feature size shrinks and the minimum separation between two wires of the same layer is getting closer. The bad-quality routing of a long wire produces excessive delay. Therefore, avoiding crosstalk for high-speed VLSI design is of growing importance. However, it is complicated and inefficient to solve the problem in conventional two-stage flow. The difficulty of minimizing crosstalk during global routing is that nets have no track information at this stage, and detailed routing is a time-consuming task. Therefore, the track assignment, an intermediate stage between global and detailed routing, is incorporated with the routing flow. This work will focus on gridless routing system, and integrate an efficient crosstalk-driven routing system, including a congestion-driven global router, a crosstalk-driven TA (GTA) and enhanced NEMO with fast PMT extraction. Experimental results show that the three stage routing is faster than the two stage routing on gridless system. In addition, a crosstalk-driven gridless track assignment will reduce crosstalk and receive a better routing result.