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dc.contributor.author曾彥勳en_US
dc.contributor.authorYan-Shiun Tzengen_US
dc.contributor.author王協源en_US
dc.contributor.authorShie-Yuan Wangen_US
dc.date.accessioned2014-12-12T03:10:24Z-
dc.date.available2014-12-12T03:10:24Z-
dc.date.issued2006en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009456515en_US
dc.identifier.urihttp://hdl.handle.net/11536/82181-
dc.description.abstract近年來,提升處理器的工作速度變的越來越難以有效改善程式的執行效能。主要的處理器製造商,如Intel、AMD等公司都進而轉往多核心處理器平台來增加額外的執行效能。因此具有多核心處理器平台的桌上型個人電腦或是筆記型電腦將會越來越普及,價錢也越來越被消費者所接受。 在這篇論文中,我們提出了新穎的平行模擬方法為了加速網路模擬器在多核心架構上的模擬速度。論文中,我們將此方法實作應用在NS2網路模擬器上並做適當的設計調整。同時,我們量測NS2網路模擬器在各種不同的模擬條件之下,效能提升的成果並且討論系統未來的擴充性與發展改善的方向。zh_TW
dc.description.abstractIn recent years increasing, CPU clock speed is becoming more and more difficult to effectively improve the performance. Major CPU venders such as Intel, AMD, etc. have all turned to multicore CPUs as the best way to gain additional performance. A desktop PC or NB which are with modern multicore systems will become more and more popular and its cost will become more and more inexpensive. This thesis presents to a novel and general parallel simulation approach to increasing network simulation speeds on modern multicore systems. In this thesis, we present the design and implementation of this approach and apply it to the NS2 network simulator. We show the achieved performance speedups of the NS2 network simulator under various network conditions. Finally, several possible future developments are proposed.en_US
dc.language.isoen_USen_US
dc.subject中央處理器zh_TW
dc.subject雙核心zh_TW
dc.subject四核心zh_TW
dc.subject多核心zh_TW
dc.subject網路模擬器zh_TW
dc.subject模擬zh_TW
dc.subject事件層平行模擬zh_TW
dc.subject執行緒zh_TW
dc.subjectCPUen_US
dc.subjectdual-coreen_US
dc.subjectquad-coreen_US
dc.subjectmulticoreen_US
dc.subjectnetwork simulatoren_US
dc.subjectsimulationen_US
dc.subjectNS2en_US
dc.subjectELPen_US
dc.subjectEvent-level Parallelismen_US
dc.subjectThreaden_US
dc.title在事件層平行方法下 NS2 網路模擬器的效能量測zh_TW
dc.titleThe Performance of the NS2 Network Simulator using the Event-level Parallelism Approachen_US
dc.typeThesisen_US
dc.contributor.department網路工程研究所zh_TW
Appears in Collections:Thesis


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