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dc.contributor.authorChiang, Meng-Hsuehen_US
dc.contributor.authorLin, Jeng-Nanen_US
dc.contributor.authorKim, Keunwooen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2014-12-08T15:10:57Z-
dc.date.available2014-12-08T15:10:57Z-
dc.date.issued2008-09-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2008.927664en_US
dc.identifier.urihttp://hdl.handle.net/11536/8391-
dc.description.abstractPragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V(T)'s for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.en_US
dc.language.isoen_USen_US
dc.subjectcorner effectsen_US
dc.subjectpolysilicon gateen_US
dc.subjecttriple-gate (TG)en_US
dc.subjectMOSFETsen_US
dc.titleOptimal design of triple-gate devices for high-performance and low-power applicationsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2008.927664en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume55en_US
dc.citation.issue9en_US
dc.citation.spage2423en_US
dc.citation.epage2428en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000258914000018-
dc.citation.woscount3-
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