Optimal design of triple-gate devices for high-performance and low-power applications

doi:10.1109/TED.2008.927664

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chiang, Meng-Hsueh	en_US
dc.contributor.author	Lin, Jeng-Nan	en_US
dc.contributor.author	Kim, Keunwoo	en_US
dc.contributor.author	Chuang, Ching-Te	en_US
dc.date.accessioned	2014-12-08T15:10:57Z	-
dc.date.available	2014-12-08T15:10:57Z	-
dc.date.issued	2008-09-01	en_US
dc.identifier.issn	0018-9383	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TED.2008.927664	en_US
dc.identifier.uri	http://hdl.handle.net/11536/8391	-
dc.description.abstract	Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V(T)'s for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.	en_US
dc.language.iso	en_US	en_US
dc.subject	corner effects	en_US
dc.subject	polysilicon gate	en_US
dc.subject	triple-gate (TG)	en_US
dc.subject	MOSFETs	en_US
dc.title	Optimal design of triple-gate devices for high-performance and low-power applications	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TED.2008.927664	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON ELECTRON DEVICES	en_US
dc.citation.volume	55	en_US
dc.citation.issue	9	en_US
dc.citation.spage	2423	en_US
dc.citation.epage	2428	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000258914000018	-
dc.citation.woscount	3	-
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