Title: Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications
Authors: Chen, Wei-Zen
Huang, Guan-Sheng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: Clock multiplier unit (CMU);parallel feedback shift register (PFSR);psuedorandom word generator (PRWG);SerDes
Issue Date: 1-Jul-2008
Abstract: This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of 2(7) - 1, 2(10) - 1, 2(15) - 1, 2(23) - 1, and 2(31) - 1 b according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 ps(rms), and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-mu m CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators.
URI: http://dx.doi.org/10.1109/TCSI.2008.916507
http://hdl.handle.net/11536/8605
ISSN: 1549-8328
DOI: 10.1109/TCSI.2008.916507
Journal: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 55
Issue: 6
Begin Page: 1495
End Page: 1501
Appears in Collections:Articles


Files in This Item:

  1. 000257711600010.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.