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dc.contributor.authorWang, Terry Tai-Juien_US
dc.contributor.authorLu, Tien-Linen_US
dc.contributor.authorWu, Chien-Hungen_US
dc.contributor.authorLiu, Yu-Chengen_US
dc.contributor.authorHung, Shih-Weien_US
dc.contributor.authorHsieh, Ing-Jaren_US
dc.contributor.authorKuo, Cheng-Tzuen_US
dc.date.accessioned2014-12-08T15:11:37Z-
dc.date.available2014-12-08T15:11:37Z-
dc.date.issued2011-05-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.50.05EF03en_US
dc.identifier.urihttp://hdl.handle.net/11536/8918-
dc.description.abstractIridium nanocrystals (Ir-NCs) lying on the Si(3)N(4)/SiO(2) tunneling layer have been demonstrated and Ir-NC-assisted thin-film transistor nonvolatile memory devices were successfully developed. Results show that Ir-NCs with a number density of similar to 6 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge trapping centers. Owing to the asymmetric SiO(2)/Si(3)N(4) tunneling layer that increases programming/erasing efficiency, a significant memory window of 5.5 V has potential to be applied to multibit memory devices. Furthermore, after 10(4) s, the memory window is still about 4.0 V in logic states. (C) 2011 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titleIridium Nanocrystal Thin-Film Transistor Nonvolatile Memory with Si(3)N(4)/SiO(2) Stack of Asymmetric Tunnel Barrieren_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.50.05EF03en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume50en_US
dc.citation.issue5en_US
dc.citation.spageen_US
dc.citation.epageen_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
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