完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Wang, Terry Tai-Jui | en_US |
dc.contributor.author | Lu, Tien-Lin | en_US |
dc.contributor.author | Wu, Chien-Hung | en_US |
dc.contributor.author | Liu, Yu-Cheng | en_US |
dc.contributor.author | Hung, Shih-Wei | en_US |
dc.contributor.author | Hsieh, Ing-Jar | en_US |
dc.contributor.author | Kuo, Cheng-Tzu | en_US |
dc.date.accessioned | 2014-12-08T15:11:37Z | - |
dc.date.available | 2014-12-08T15:11:37Z | - |
dc.date.issued | 2011-05-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1143/JJAP.50.05EF03 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/8918 | - |
dc.description.abstract | Iridium nanocrystals (Ir-NCs) lying on the Si(3)N(4)/SiO(2) tunneling layer have been demonstrated and Ir-NC-assisted thin-film transistor nonvolatile memory devices were successfully developed. Results show that Ir-NCs with a number density of similar to 6 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge trapping centers. Owing to the asymmetric SiO(2)/Si(3)N(4) tunneling layer that increases programming/erasing efficiency, a significant memory window of 5.5 V has potential to be applied to multibit memory devices. Furthermore, after 10(4) s, the memory window is still about 4.0 V in logic states. (C) 2011 The Japan Society of Applied Physics | en_US |
dc.language.iso | en_US | en_US |
dc.title | Iridium Nanocrystal Thin-Film Transistor Nonvolatile Memory with Si(3)N(4)/SiO(2) Stack of Asymmetric Tunnel Barrier | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1143/JJAP.50.05EF03 | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS | en_US |
dc.citation.volume | 50 | en_US |
dc.citation.issue | 5 | en_US |
dc.citation.spage | en_US | |
dc.citation.epage | en_US | |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
顯示於類別: | 期刊論文 |