Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 李毅郎 | en_US |
| dc.contributor.author | Li Yih-Lang | en_US |
| dc.date.accessioned | 2014-12-13T10:29:31Z | - |
| dc.date.available | 2014-12-13T10:29:31Z | - |
| dc.date.issued | 2006 | en_US |
| dc.identifier.govdoc | NSC95-2220-E009-019 | zh_TW |
| dc.identifier.uri | http://hdl.handle.net/11536/89354 | - |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=1279620&docId=234488 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.title | 單晶片系統驗證之核心技術開發---子計畫五：系統晶片布局設計後之驗證與最佳化平台研究(II) | zh_TW |
| dc.title | Post-Layout Verification and Optimization Platform(II) | en_US |
| dc.type | Plan | en_US |
| dc.contributor.department | 國立交通大學資訊工程學系(所) | zh_TW |
| Appears in Collections: | Research Plans | |
