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dc.contributor.authorWeng, Yi-Hsinen_US
dc.contributor.authorTsai, Hui-Wenen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:11:39Z-
dc.date.available2014-12-08T15:11:39Z-
dc.date.issued2011-05-01en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.microrel.2010.12.016en_US
dc.identifier.urihttp://hdl.handle.net/11536/8938-
dc.description.abstractA new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage to drive a capacitive output load, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide overstress problem, the new proposed charge pump circuit is suitable for applications in low-voltage CMOS IC products. (C) 2011 Elsevier Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleDesign to suppress return-back leakage current of charge pump circuit in low-voltage CMOS processen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.microrel.2010.12.016en_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.citation.volume51en_US
dc.citation.issue5en_US
dc.citation.spage871en_US
dc.citation.epage878en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000290245700001-
dc.citation.woscount1-
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